Specific ResponsibilitiesResponsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.Develop and implement low-power DFT architecture and infrastructure.Generate structural test vectors, analyze and improve coverage, test time and test cost.Perform pre/post-layout scan and MBIST simulations.Work with designers on STA, physical, power and logical issues related to DFT.Work with test engineers to bring up test vectors on silicon.Specific ResponsibilitiesResponsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.Develop and implement low-power DFT architecture and infrastructure.Generate structural test vectors, analyze and improve coverage, test time and test cost.Perform pre/post-layout scan and MBIST simulations.Work with designers on STA, physical, power and logical issues related to DFT.Work with test engineers to bring up test vectors on silicon.

Specific Responsibilities

Specific ResponsibilitiesSpecific Responsibilities

• Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.

Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.

• Develop and implement low-power DFT architecture and infrastructure.

Develop and implement low-power DFT architecture and infrastructure.

• Generate structural test vectors, analyze and improve coverage, test time and test cost.

Generate structural test vectors, analyze and improve coverage, test time and test cost.

• Perform pre/post-layout scan and MBIST simulations.

Perform pre/post-layout scan and MBIST simulations.

• Work with designers on STA, physical, power and logical issues related to DFT.

Work with designers on STA, physical, power and logical issues related to DFT.

• Work with test engineers to bring up test vectors on silicon.

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