STAFF ENGINEER - HBM VERIFICATION

Department Introduction

We are a global engineering team developing advanced High Bandwidth Memory (HBM) and emerging memory solutions. We collaborate across build and verification fields to innovate, solve complex technical challenges, and deliver efficient, high-quality products that advance memory performance!

Position Overview

As a STAFF ENGINEER - HBM VERIFICATION, you will lead pre-silicon verification and detailed end-to-end assessment of sophisticated, full-chip custom inventions that include advanced low-power and power-management technologies. Your role will enhance functional coverage, improve design quality, and influence the evolution of current and future HBM architectures. You will work with knowledgeable colleagues across global teams while continuing to learn and expand your technical contributions.

Responsibilities

• Lead verification strategy and execution for complex, full-chip custom builds, including low-power and power-management functionality.
• Simulate, analyze, and debug pre-silicon builds to identify functional issues and drive timely resolution.
• Build test cases, stimulus, testbenches, and test vectors that advance functional coverage for HBM and emerging memory architectures.
• Build and improve verification methodologies, simulation environments, regression flows, and coverage-analysis processes to increase efficiency and design quality.
• Collaborate across global build and verification teams, applying AI-assisted tools where appropriate to streamline regression triage, technical analysis, documentation, and other engineering workflows.

Minimum Qualifications

• Bachelor’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field.
• Eight or more years of experience in pre-silicon verification, including simulation and debugging of complex digital or full-chip builds.
• Proficiency in developing and simulating verification environments, testbenches, test cases, and stimulus.
• Experience analyzing digital circuits, troubleshooting simulation results, and improving functional coverage through structured problem-solving.
• Experience leading technical verification activities and collaborating with cross-functional or geographically distributed engineering teams.

Preferred Qualifications

• Experience applying Universal Verification Methodology (UVM) in verification environments.
• Knowledge of Build for Testability (BFT), including custom BFT features and standard scan-chain methodologies.
• Experience with critical-path or data-path timing analysis in complex integrated-circuit builds.
• Experience verifying full-chip custom builds with power, performance, bandwidth, or low-power requirements.
• Experience bringing to bear AI-enabled or automation tools to improve verification efficiency, analysis, or engineering workflows.