Staff Engineer - Analog Layout

Key Responsibilities

Technical Ownership

• Lead full‑custom layout for complex Analog / Mixed‑Signal IP blocks, including but not limited to:
  • Bandgap references, LDOs and regulators, Charge pumps (positive/negative)
  • PLLs, delay lines, oscillators, IO & PHY‑related analog blocks
  • Temperature sensors, bias circuits
  • ESD protection devices and clamps
• Own layout quality from floor‑planning to tape‑out, ensuring:
  • Device matching and symmetry, noise isolation and substrate strategies
  • Robust power/ground planning
  • Yield, reliability, and DFM compliance
• Work closely with circuit designers to translate performance goals into layout strategies, especially in noise‑sensitive mixed‑signal environments.

Advanced Technology Expertise

• Strong experience in advanced FinFET nodes such as TSMC 3nm, 5nm, including:
  • Fin quantization awareness
  • Multi‑Vt, multi‑fin strategies
  • Advanced metal stack planning
• Solid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm) for analog robustness and legacy IP support.
• Deep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.

Layout Verification & Signoff

• Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks.
• Review and address issues related to:
  • EM/IR, latch‑up, ESD window compliance
  • Device stress and matching degradation
• Interface with foundry and CAD teams for waiver management and signoff convergence.

Leadership & Mentorship

• Provide technical guidance and design reviews for junior and mid‑level layout engineers.
• Establish and document best‑known methods (BKMs) for AMS layout across nodes.
• Drive IP reuse, layout template development, and methodology improvements.