Staff Application Engineer- Physical Design

Job Description and Requirements We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.What You'll Be DoingSupport customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designsDebug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and belowDevelop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedulesRun benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologiesCollaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requestsPresent technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yieldTravel to customer sites as needed to provide onsite support, training, and design reviewsThe Impact You Will HaveAccelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategiesEnable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewalsShape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teamsBuild deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flowsReduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practicesContribute to the success of chips that will ship in millions of devices, from mobile processors to AI acceleratorsHelp customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioningWhat You'll NeedBachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ yearsDeep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routingStrong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodesProficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysisSolid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigrationExperience with logical and physical synthesis flows and AI-driven methodologies for optimizationExcellent communication skills with the ability to present technical concepts clearly to both engineering teams and managementWho You AreYou can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problemComfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depthYou explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision todayCustomer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forwardYou document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff callEnergized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forwardThe Team You'll Be Part OfYou will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.Job Description and Requirements We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.What You'll Be DoingSupport customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designsDebug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and belowDevelop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedulesRun benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologiesCollaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requestsPresent technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yieldTravel to customer sites as needed to provide onsite support, training, and design reviewsThe Impact You Will HaveAccelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategiesEnable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewalsShape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teamsBuild deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flowsReduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practicesContribute to the success of chips that will ship in millions of devices, from mobile processors to AI acceleratorsHelp customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioningWhat You'll NeedBachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ yearsDeep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routingStrong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodesProficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysisSolid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigrationExperience with logical and physical synthesis flows and AI-driven methodologies for optimizationExcellent communication skills with the ability to present technical concepts clearly to both engineering teams and managementWho You AreYou can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problemComfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depthYou explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision todayCustomer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forwardYou document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff callEnergized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forwardThe Team You'll Be Part OfYou will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.Job Description and Requirements We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.What You'll Be DoingSupport customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designsDebug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and belowDevelop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedulesRun benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologiesCollaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requestsPresent technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yieldTravel to customer sites as needed to provide onsite support, training, and design reviewsThe Impact You Will HaveAccelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategiesEnable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewalsShape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teamsBuild deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flowsReduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practicesContribute to the success of chips that will ship in millions of devices, from mobile processors to AI acceleratorsHelp customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioningWhat You'll NeedBachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ yearsDeep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routingStrong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodesProficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysisSolid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigrationExperience with logical and physical synthesis flows and AI-driven methodologies for optimizationExcellent communication skills with the ability to present technical concepts clearly to both engineering teams and managementWho You AreYou can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problemComfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depthYou explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision todayCustomer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forwardYou document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff callEnergized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forwardThe Team You'll Be Part OfYou will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Job Description and RequirementsWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.What You'll Be DoingSupport customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designsDebug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and belowDevelop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedulesRun benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologiesCollaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requestsPresent technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yieldTravel to customer sites as needed to provide onsite support, training, and design reviewsThe Impact You Will HaveAccelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategiesEnable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewalsShape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teamsBuild deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flowsReduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practicesContribute to the success of chips that will ship in millions of devices, from mobile processors to AI acceleratorsHelp customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioningWhat You'll NeedBachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ yearsDeep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routingStrong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodesProficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysisSolid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigrationExperience with logical and physical synthesis flows and AI-driven methodologies for optimizationExcellent communication skills with the ability to present technical concepts clearly to both engineering teams and managementWho You AreYou can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problemComfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depthYou explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision todayCustomer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forwardYou document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff callEnergized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forwardThe Team You'll Be Part OfYou will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We Are

We AreWe Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You AreYou Are

You have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.

You have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill a tapeout schedule. You know the difference between a flow that works on paper and one that actually closes timing at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.You have spent years in the trenches of physical design, where a bad placement decision at 5nm costs weeks and a routing congestion hotspot can kill atapeoutschedule. You know the difference between a flow that works on paper and one thatactually closestiming at advanced nodes, and you have lived through enough iterations to spot the gap before it becomes a crisis. You are the engineer who gets called when a customer's design is stuck at 87% routing utilization or when their clock tree is burning 200mW more than it should, and you do not just debug the problem, you teach them how to think differently about their methodology.

Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.

Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, and work the problem until it is solved or until you have a clear path to escalation.Working directly with customers energizes you. You like the puzzle of understanding their constraints, their schedule pressure, their process quirks, and then translating that into a concrete plan using Fusion Compiler or ICC2 that actually moves their design forward. You do not need a perfect runbook to be effective. You ask the right questions, reproduce the issue, andworkthe problem until it is solved or until you have a clear path to escalation.

At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.

At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.At Synopsys, you will be the technical bridge between our tools and the customers building the chips that power everything. The work is real, the problems are hard, and the impact is immediate.

What You'll Be Doing

What You'll Be DoingWhat You'll Be Doing

• Support customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designs

Support customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designsSupport customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler, helping them achieve PPA targets on advanced node designs

• Debug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and below

Debug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and belowDebug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and below

• Develop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedules

Develop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedulesDevelop and deliver methodology recommendations tailored to customer design constraints, process technologies, and project schedules

• Run benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologies

Run benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologiesRun benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologies

• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requests

Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requestsCollaborate with R&D, product management, and field teams to translate customer pain points into product requirements and feature requests

• Present technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yield

Present technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yieldPresent technical content to customer engineering teams and management, translating tool capabilities into business outcomes like reduced cycle time or improved yield

• Travel to customer sites as needed to provide onsite support, training, and design reviews

Travel to customer sites as needed to provide onsite support, training, and design reviewsTravel to customer sites as needed to provide onsite support, training, and design reviews

The Impact You Will Have

The Impact You Will HaveThe Impact You Will Have

• Accelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategies

Accelerate customer tapeout schedules by weeks through targeted methodology improvements and tool optimization strategiesAccelerate customertapeoutschedules by weeks through targeted methodology improvements and tool optimization strategies

• Enable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewals

Enable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewalsEnable successful adoption of Synopsys tools at key accounts, directly influencing design wins and renewals

• Shape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teams

Shape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teamsShape product roadmaps by surfacing real-world customer challenges and advanced node requirements to engineering teams

• Build deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flows

Build deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flowsBuild deep technical relationships with leading semiconductor companies, becoming their trusted advisor on physical design flows

• Reduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practices

Reduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practicesReduce customer support escalations by proactively addressing methodology gaps and training engineering teams on best practices

• Contribute to the success of chips that will ship in millions of devices, from mobile processors to AI accelerators

Contribute to the success of chips that will ship in millions of devices, from mobile processors to AI acceleratorsContribute to the success of chips that will ship in millions of devices, from mobile processors to AI accelerators

• Help customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioning

Help customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioningHelp customers unlock the full value of their Synopsys investment, improving their ROI and competitive positioning

What You'll Need

What You'll NeedWhat You'll Need

• Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years

Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ yearsBachelor's degree in Electrical Engineeringor equivalent with 7+ years of hands-on ASIC physical design experience, orMaster'sdegree with 5+ years

• Deep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routing

Deep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routingDeep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routing

• Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodes

Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodesStrong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodes

• Proficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysis

Proficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysisProficiency with static timing analysis tools, particularlyPrimeTime, including setup/hold analysis and noise analysis

• Solid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigration

Solid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigrationSolid understanding of advanced node design challenges at 7nm and below, includingFinFETeffects, multi-patterning, and electromigration

• Experience with logical and physical synthesis flows and AI-driven methodologies for optimization

Experience with logical and physical synthesis flows and AI-driven methodologies for optimizationExperience with logical and physical synthesis flows and AI-driven methodologies for optimization

• Excellent communication skills with the ability to present technical concepts clearly to both engineering teams and management

Excellent communication skills with the ability to present technical concepts clearly to both engineering teams and managementExcellent communication skills with the ability to present technical concepts clearly to both engineering teams and management

Who You Are

Who You AreWho You Are

• You can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problem

You can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problemYou can walk into a customer war room where timing is failing by 500ps at sign-off and quickly triage whether it is a methodology issue, a tool setting, or a fundamental design problem

• Comfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depth

Comfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depthComfortable context-switching between multiple customer engagements, you manage priorities without dropping threads or losing technical depth

• You explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision today

You explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs to make a decision todayYou explain complex tradeoffs like CTS topology choices or placement density targets in ways that make sense to a design lead who needs tomake a decisiontoday

• Customer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forward

Customer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forwardCustomer-focused without being a pushover, you push back when a request does not align with best practices and offer a better path forward

• You document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff call

You document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff callYou document your work clearly enough that another engineer or the customer can pick up where you left off without a two-hour handoff call

• Energized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forward

Energized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forwardEnergized by teaching, you genuinely enjoy the moment when a customer engineer understands why their flow was suboptimal and how to fix it going forward

The Team You'll Be Part Of

The Team You'll Be Part OfThe Team You'll Be Part Of

You will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.

You will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.You will join the Customer Success Group, the team responsible for ensuring customers get maximum value from Synopsys physical design tools. This is a technical applications role working directly with semiconductor companies on their most challenging designs. You will collaborate closely with field sales, R&D engineering, and product management teams across Synopsys to deliver customer success and drive product adoption.

Rewards and Benefits

Rewards and BenefitsRewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

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