Job description
About onsemi
onsemi is driving innovation in power, sensing, and automotive semiconductor solutions to enable a more sustainable future. Our Treo™ platform underpins next-generation intelligent power systems for automotive and industrial markets, emphasizing safety, reliability, and scalability.
Role Overview
We are seeking a senior Digital Design Member of Technical Staff (MTS) to lead and deliver digital controller IP for power, clock, and error management subsystems within the onsemi Treo™ platform. This role is a hands-on technical leadership position, focused on architecting, designing, integrating, and evolving complex digital IP that tightly interfaces with analog and mixed-signal blocks in automotive-grade SoCs.
The successful candidate will bring deep experience in automotive functional safety, digital-analog co-design, and system-level integration, while also serving as a technical mentor and thought leader within the Cork design organization.
Key Responsibilities
- Architect, design, and implement digital system controllers for:
Power management
Clock management
Error detection, reporting, and mitigation subsystems
- Develop robust digital IP that controls and interacts closely with analog and mixed-signal blocks.
- Own IP delivery from architecture through RTL, verification, integration, and silicon bring-up support.
- Drive and support digital-on-top product integration flows, including:
IP integration into SoC environments
Clocking, reset, power domain, and safety integration
- Ensure designs meet automotive functional safety requirements (e.g., ISO 26262 concepts such as ASIL, fault coverage, diagnostic mechanisms).
- Collaborate cross-functionally with:
Analog design
Verification
Physical design
Systems, safety, and product engineering teams
- Define and evolve IP roadmaps aligned with:
Platform strategy
Product requirements
Long-term business objectives
- Mentor and technically guide junior and mid-level engineers, promoting best practices in design, documentation, and review culture.
- Contribute to continuous improvement of:
Design methodologies
Verification strategies
Automation and productivity tools
Stay technically curious and engaged with emerging AI/ML applications in digital design, including their potential impact on RTL development, verification, and productivity.
Required Qualifications
- 15+ years of hands-on digital design experience, primarily in ASIC or SoC development.
- Proven experience delivering automotive IP with functional safety requirements.
- Strong background designing digital controllers for analog blocks (e.g., power regulators, PLLs, sensors, clocking systems).
- Deep understanding of system-level digital integration, including:
- Power and clock domain management
- Reset strategies
- Error handling and safety mechanisms
- Solid experience with RTL design (SystemVerilog).
- Working knowledge of constrained-random verification methodologies, including SystemVerilog and UVM.
- Demonstrated ability to work effectively as a senior individual contributor, owning complex technical problems end to end.
Strong communication skills and a demonstrated willingness to mentor junior engineers.
Preferred / Plus Qualifications
- Experience with automotive safety standards such as ISO 26262 (concept, system, or IP-level application).
- Working knowledge of JIRA for task tracking and JAMA for requirements management.
- Exposure to safety diagnostics, fault injection, or safety verification techniques.
- Experience contributing to platform-level IP strategies or multi-generation roadmap planning.
- Familiarity with low-power design techniques and power-aware verification.
What We Offer
- Opportunity to work on industry-leading automotive and power semiconductor platforms.
- A senior, high-impact technical role with architectural ownership.
- A collaborative engineering culture with strong ties between digital, analog, and system teams.
- Competitive compensation and benefits.
- Career growth within a global semiconductor leader, while being based in Cork’s vibrant technology ecosystem.