SIC Physical Design, Manager

Job Description and Requirements Alternate Job TitlesPhysical Design LeadASIC Physical Design ManagerBackend Design ManagerPlace and Route ManagerPhysical Implementation ManagerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.What You'll Be DoingLead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-outDrive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nmOwn timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrityBuild, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levelsCollaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestonesChampion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design qualityThe Impact You Will HaveDeliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructureSet the standard for advanced-node physical design quality and methodology across Synopsys silicon engineeringDrive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon successShape the physical design tool flows, automation frameworks, and best practices adopted across the organizationGrow a team of engineers who become the next generation of technical leaders in physical designAdvance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systemsWhat You'll Need10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closureProven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outsExpert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawkStrong scripting and automation skills in Tcl, Python, and Perl for flow developmentBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plusExperience managing and mentoring engineering teams with a history of developing talentWho You AreYou can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hearYou build teams by teaching people how to think through a problem, not just how to run a toolYou manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team downWhen a design is stuck, you make a call with the information you have and move forward with a plan the team can executeThe Team You'll Be Part OfYou will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesPhysical Design LeadASIC Physical Design ManagerBackend Design ManagerPlace and Route ManagerPhysical Implementation ManagerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.What You'll Be DoingLead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-outDrive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nmOwn timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrityBuild, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levelsCollaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestonesChampion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design qualityThe Impact You Will HaveDeliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructureSet the standard for advanced-node physical design quality and methodology across Synopsys silicon engineeringDrive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon successShape the physical design tool flows, automation frameworks, and best practices adopted across the organizationGrow a team of engineers who become the next generation of technical leaders in physical designAdvance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systemsWhat You'll Need10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closureProven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outsExpert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawkStrong scripting and automation skills in Tcl, Python, and Perl for flow developmentBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plusExperience managing and mentoring engineering teams with a history of developing talentWho You AreYou can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hearYou build teams by teaching people how to think through a problem, not just how to run a toolYou manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team downWhen a design is stuck, you make a call with the information you have and move forward with a plan the team can executeThe Team You'll Be Part OfYou will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesPhysical Design LeadASIC Physical Design ManagerBackend Design ManagerPlace and Route ManagerPhysical Implementation ManagerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.What You'll Be DoingLead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-outDrive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nmOwn timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrityBuild, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levelsCollaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestonesChampion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design qualityThe Impact You Will HaveDeliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructureSet the standard for advanced-node physical design quality and methodology across Synopsys silicon engineeringDrive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon successShape the physical design tool flows, automation frameworks, and best practices adopted across the organizationGrow a team of engineers who become the next generation of technical leaders in physical designAdvance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systemsWhat You'll Need10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closureProven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outsExpert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawkStrong scripting and automation skills in Tcl, Python, and Perl for flow developmentBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plusExperience managing and mentoring engineering teams with a history of developing talentWho You AreYou can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hearYou build teams by teaching people how to think through a problem, not just how to run a toolYou manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team downWhen a design is stuck, you make a call with the information you have and move forward with a plan the team can executeThe Team You'll Be Part OfYou will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Job Description and RequirementsAlternate Job TitlesPhysical Design LeadASIC Physical Design ManagerBackend Design ManagerPlace and Route ManagerPhysical Implementation ManagerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.What You'll Be DoingLead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-outDrive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nmOwn timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrityBuild, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levelsCollaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestonesChampion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design qualityThe Impact You Will HaveDeliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructureSet the standard for advanced-node physical design quality and methodology across Synopsys silicon engineeringDrive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon successShape the physical design tool flows, automation frameworks, and best practices adopted across the organizationGrow a team of engineers who become the next generation of technical leaders in physical designAdvance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systemsWhat You'll Need10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closureProven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outsExpert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawkStrong scripting and automation skills in Tcl, Python, and Perl for flow developmentBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plusExperience managing and mentoring engineering teams with a history of developing talentWho You AreYou can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hearYou build teams by teaching people how to think through a problem, not just how to run a toolYou manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team downWhen a design is stuck, you make a call with the information you have and move forward with a plan the team can executeThe Team You'll Be Part OfYou will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Alternate Job TitlesPhysical Design LeadASIC Physical Design ManagerBackend Design ManagerPlace and Route ManagerPhysical Implementation ManagerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.What You'll Be DoingLead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-outDrive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nmOwn timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrityBuild, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levelsCollaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestonesChampion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design quality

Alternate Job Titles

Alternate Job TitlesAlternate Job Titles

• Physical Design Lead

Physical Design LeadPhysical Design Lead

• ASIC Physical Design Manager

ASIC Physical Design ManagerASIC Physical Design Manager

• Backend Design Manager

Backend Design ManagerBackend Design Manager

• Place and Route Manager

Place and Route ManagerPlace and Route Manager

• Physical Implementation Manager

Physical Implementation ManagerPhysical Implementation Manager

We Are

We AreWe Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You AreYou Are

You have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.

You have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months in respins is usually a decision made during floorplanning that nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.You have spent a decade in physical design, and you know that the difference between a chip that tapes out clean and one that burns months inrespinsis usually a decision made duringfloorplanningthat nobody questioned hard enough. You are the person who questions it. You have closed timing on designs running north of 2 GHz, and you understand that at those frequencies, every picosecond matters and every SI issue that looks small in simulation becomes a showstopper in silicon.

Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.

Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.Managing a team is not about delegation for you. It is about building engineers who can see three steps ahead, who understand why a clock tree decision today affects yield six months from now. You are comfortable in the gap between what the spec says and what will actually work. When a design review surfaces a conflict between performance targets and physical constraints, you pull the right people together, sketch the tradeoffs, and drive to a decision the team can execute against.

You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.

You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler, PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.You know the Synopsys toolchain deeply because you have lived in it. ICC2, Fusion Compiler,PrimeTime, these are instruments you have tuned to deliver results on 7nm, 5nm, and 3nm nodes where the margin for error is measured in atoms. At Synopsys, you will lead physical design for the interconnect technology that makes AI infrastructure possible.

What You'll Be Doing

What You'll Be DoingWhat You'll Be Doing

• Lead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-out

Lead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-outLead the complete physical design flow for high-speed die-to-die interconnect chips operating at 2 GHz and above, from RTL handoff through tape-out

• Drive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nm

Drive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nmDrivefloorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on advanced nodes including 7nm, 5nm, and 3nm

• Own timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrity

Own timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrityOwn timing closure across all corners and modes, working with front-end teams to resolve critical paths and ensure SI/PI integrity

• Build, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levels

Build, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levelsBuild, manage, and mentor a global physical design team, setting technical direction and developing engineers at multiple levels

• Collaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestones

Collaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestonesCollaborate with architecture, design, verification, and package teams to align physical implementation with product requirements and manage milestones

• Champion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design quality

Champion automation and methodology improvements using Tcl, Python, and Perl scripts that increase team productivity and design qualityChampion automation and methodology improvements usingTcl, Python, and Perl scripts that increase team productivity and design qualityThe Impact You Will HaveDeliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructureSet the standard for advanced-node physical design quality and methodology across Synopsys silicon engineeringDrive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon successShape the physical design tool flows, automation frameworks, and best practices adopted across the organizationGrow a team of engineers who become the next generation of technical leaders in physical designAdvance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systemsWhat You'll Need10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closureProven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outsExpert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawkStrong scripting and automation skills in Tcl, Python, and Perl for flow developmentBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plusExperience managing and mentoring engineering teams with a history of developing talentWho You AreYou can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hearYou build teams by teaching people how to think through a problem, not just how to run a toolYou manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team downWhen a design is stuck, you make a call with the information you have and move forward with a plan the team can executeThe Team You'll Be Part Of

The Impact You Will Have

The Impact You Will HaveThe Impact You Will Have

• Deliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructure

Deliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructureDeliver the physical implementation for high-bandwidth, ultra-low latency chip-to-chip communication that powers AI training and inference infrastructure

• Set the standard for advanced-node physical design quality and methodology across Synopsys silicon engineering

Set the standard for advanced-node physical design quality and methodology across Synopsys silicon engineeringSet the standard for advanced-node physical design quality and methodology across Synopsys silicon engineering

• Drive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon success

Drive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon successDrive multiple successful tape-outs on cutting-edge process nodes, ensuring first-pass silicon success

• Shape the physical design tool flows, automation frameworks, and best practices adopted across the organization

Shape the physical design tool flows, automation frameworks, and best practices adopted across the organizationShape the physical design tool flows, automation frameworks, and best practices adopted across the organization

• Grow a team of engineers who become the next generation of technical leaders in physical design

Grow a team of engineers who become the next generation of technical leaders in physical designGrow a team of engineers who become the next generation of technical leaders in physical design

• Advance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systems

Advance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systemsAdvance Synopsys' position as a leader in AI silicon innovation through interconnect technology that enables next-generation systems

What You'll Need

What You'll NeedWhat You'll Need

• 10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closure

10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closure10+ years of hands-on experience in physical design with deep expertise in high-frequency chip implementation and timing closure

• Proven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outs

Proven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outsProven track record leading physical design on advanced process nodes including 7nm, 5nm, or 3nm with multiple successful tape-outs

• Expert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawk

Expert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler, PrimeTime, StarRC, and RedHawkExpert-level proficiency with Synopsys physical design tools including ICC2, Fusion Compiler,PrimeTime,StarRC, and RedHawk

• Strong scripting and automation skills in Tcl, Python, and Perl for flow development

Strong scripting and automation skills in Tcl, Python, and Perl for flow developmentStrong scripting and automation skills inTcl, Python, and Perl for flow development

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plus

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plusBachelor's orMaster's degree in Electrical Engineering, Computer Engineering, or related field, PhD is a strong plus

• Experience managing and mentoring engineering teams with a history of developing talent

Experience managing and mentoring engineering teams with a history of developing talentExperience managing and mentoring engineering teams with a history of developing talent

Who You Are

Who You AreWho You Are

• You can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hear

You can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hearYou can spot the physical constraint that will break the schedule in three weeks and explain the fix to both the engineer and the program manager in terms each needs to hear

• You build teams by teaching people how to think through a problem, not just how to run a tool

You build teams by teaching people how to think through a problem, not just how to run a toolYou build teams by teaching people how to think through a problem, not just how to run a tool

• You manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team down

You manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team downYou manage multiple tape-outs across geographies without losing track of critical milestones or creating process overhead that slows the team down

• When a design is stuck, you make a call with the information you have and move forward with a plan the team can execute

When a design is stuck, you make a call with the information you have and move forward with a plan the team can executeWhen a design is stuck, you make a call with the information you have and move forward with a plan the team can execute

The Team You'll Be Part Of

The Team You'll Be Part OfThe Team You'll Be Part Of

You will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.

You will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.You will join a global Silicon Engineering team focused on AI silicon and high-speed interconnect technologies. The team collaborates across functions and geographies, working closely with architecture, design, verification, and product teams to deliver the physical implementation for chips that enable the next generation of AI infrastructure.

Rewards and Benefits

Rewards and BenefitsRewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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