Senior Manager, Validation Engineering

Senior Manager, Validation EngineeringAtlanta, GA or San Jose, CA (Hybrid: 3 days/week in office)Overview Join a premier chip and silicon IP provider's Memory Interface Chip business unit. Work with leading inventors and engineers to develop products that enhance data speed and security. This full-time role involves managing a team to validate and characterize high-quality memory buffer chips. Requires expertise in processor-memory interfaces, DDR topologies and protocols, high-speed signaling, signal integrity, and power integrity.ResponsibilitiesPartner with cross-functional teams including design, architecture, verification, and operations to deliver products.Own and improve validation methodologies for enhanced coverage and faster time-to-market.Manage bench validation team; perform hands-on validation and characterization (20-30% daily).Develop software for lab automation.Collaborate with external partners on test equipment, PCB manufacturing, and assembly.Handle project planning, resource allocation, and budgeting.Grow the team (current size: 12-15; plan to add 2-3 reports).RequirementsQualificationsB.S. or M.S. in Electrical Engineering.Track record of growing teams with focus on organization and methodology development.Expert Python programming for validation automation and data analysis.Knowledge of processor/memory architecture and specifications.Experience in bench testing; ATE or system testing a plus.Strong in DDR4/DDR5 bench validation and electrical characterization.SerDes, PCIe, or PHY experience preferred.Leadership experience managing 2-5+ reports or demonstrated in IC roles; hands-on technical leaders preferred (30-40% lab/bench work, scripting).Ideal from mid-sized or smaller companies.BenefitsCompensation Base: Midpoint ~$193k, based on experience. Bonus: 20%. RSUs: $145K vesting over 4 years. Benefits: 401(k) match, employee stock purchase plan, medical/dental, PTO, gym membership.Senior Manager, Validation EngineeringAtlanta, GA or San Jose, CA (Hybrid: 3 days/week in office)Overview Join a premier chip and silicon IP provider's Memory Interface Chip business unit. Work with leading inventors and engineers to develop products that enhance data speed and security. This full-time role involves managing a team to validate and characterize high-quality memory buffer chips. Requires expertise in processor-memory interfaces, DDR topologies and protocols, high-speed signaling, signal integrity, and power integrity.ResponsibilitiesPartner with cross-functional teams including design, architecture, verification, and operations to deliver products.Own and improve validation methodologies for enhanced coverage and faster time-to-market.Manage bench validation team; perform hands-on validation and characterization (20-30% daily).Develop software for lab automation.Collaborate with external partners on test equipment, PCB manufacturing, and assembly.Handle project planning, resource allocation, and budgeting.Grow the team (current size: 12-15; plan to add 2-3 reports).

Senior Manager, Validation Engineering

Senior Manager, Validation EngineeringSenior Manager, Validation Engineering

Atlanta, GA or San Jose, CA (Hybrid: 3 days/week in office)

Atlanta, GA or San Jose, CA (Hybrid: 3 days/week in office)

Overview Join a premier chip and silicon IP provider's Memory Interface Chip business unit. Work with leading inventors and engineers to develop products that enhance data speed and security. This full-time role involves managing a team to validate and characterize high-quality memory buffer chips. Requires expertise in processor-memory interfaces, DDR topologies and protocols, high-speed signaling, signal integrity, and power integrity.

OverviewOverviewJoin a premier chip and silicon IP provider's Memory Interface Chip business unit. Work with leading inventors and engineers to develop products that enhance data speed and security. This full-time role involves managing a team to validate and characterize high-quality memory buffer chips. Requires expertise in processor-memory interfaces, DDR topologies and protocols, high-speed signaling, signal integrity, and power integrity.

Responsibilities

ResponsibilitiesResponsibilities

• Partner with cross-functional teams including design, architecture, verification, and operations to deliver products.

Partner with cross-functional teams including design, architecture, verification, and operations to deliver products.

• Own and improve validation methodologies for enhanced coverage and faster time-to-market.

Own and improve validation methodologies for enhanced coverage and faster time-to-market.

• Manage bench validation team; perform hands-on validation and characterization (20-30% daily).

Manage bench validation team; perform hands-on validation and characterization (20-30% daily).

• Develop software for lab automation.

Develop software for lab automation.

• Collaborate with external partners on test equipment, PCB manufacturing, and assembly.

Collaborate with external partners on test equipment, PCB manufacturing, and assembly.

• Handle project planning, resource allocation, and budgeting.

Handle project planning, resource allocation, and budgeting.

• Grow the team (current size: 12-15; plan to add 2-3 reports).

Grow the team (current size: 12-15; plan to add 2-3 reports).