Senior Layout Designer - Pathfinding

Our semiconductor design team develops advanced memory and logic solutions that power a wide range of computing applications. Working in a highly collaborative environment, team members partner across design, technology development, verification, and CAD teams to deliver innovative, high-quality products. This role provides an opportunity to gain hands-on experience with industry-leading design methodologies and EDA tools while contributing to next-generation semiconductor technologies.

As a Layout Designer, you will support the development and preparation of multi-dimensional layouts and detailed drawings of semiconductor devices based on schematics and geometry provided by design engineers. You will work closely with experienced engineers to verify layout accuracy, perform physical verification analysis, and contribute to layout quality and efficiency initiatives. The ideal candidate is a self-motivated learner with strong problem-solving skills, attention to detail, and an interest in semiconductor design technologies.

Responsibilities

• Develop and maintain semiconductor layout designs and detailed drawings using industry-standard EDA tools while ensuring compliance with design rules and layout requirements.
• Perform layout verification, debugging, and data integrity checks, collaborating with design, verification, technology development, and CAD teams to resolve issues.
• Support floor-planning, signal-planning, and power-planning activities for assigned design blocks and product revisions.
• Contribute to layout methodology improvements, automation initiatives, and workflow enhancements, including leveraging AI-enabled tools to improve layout productivity and design efficiency.
• Participate in a globally distributed design environment and communicate technical progress, risks, and solutions effectively with cross-functional teams.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical field.
• Coursework, academic projects, internships, or research experience related to semiconductor device design, IC layout, VLSI design, or microelectronics.
• Basic knowledge of semiconductor design principles, physical layout concepts, and design rule compliance.
• Experience using or exposure to EDA tools such as Cadence Virtuoso, Synopsys tools, Calibre, or equivalent through coursework, research, or internship experience.
• Demonstrated problem-solving skills and the ability to analyze, debug, and resolve technical issues in a collaborative engineering environment.

Preferred Qualifications

• Internship, co-op, research, or project experience involving custom IC layout, physical design, or semiconductor product development.
• Familiarity with memory technologies such as NAND, DRAM, and/or SRAM.
• Experience with scripting or programming languages such as Python, Perl, Tcl, or similar automation tools.
• Exposure to physical verification methodologies, including DRC, LVS, and layout debugging techniques.
• Experience applying AI, Generative AI, or AI-assisted tools to improve engineering workflows, automation, data analysis, or design productivity.