Senior Formal Verification Engineer

Define and execute formal verification strategies for complex IPs, subsystems, and SoCs. Develop formal verification plans based on architecture and microarchitecture specifications. Create SystemVerilog Assertions (SVA), formal properties, assumptions, covers, and checkers. Debug counterexamples and work closely with designers to root-cause and resolve design issues. Drive verification closure through proof convergence, coverage analysis, and methodology improvements. Develop reusable formal verification components, libraries, and automation flows. Contribute to formal verification methodology evolution, AI-assisted verification workflows, and best practices. Mentor early career engineers and review verification plans, properties, and results. Collaborate with cross-functional teams including Architecture, RTL Design, DV, Emulation, and Silicon Validation. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 7+ years of experience in semiconductor verification with significant focus on Formal Verification. Strong understanding of: Digital Design Fundamentals Computer Architecture and SoC Design Expertise in SystemVerilog and SystemVerilog Assertions (SVA). Hands-on experience with formal verification tools such as: Cadence JasperGold Synopsys VC Formal Strong debugging and analytical skills.