R&D Engineering, Sr Engineer

ActiveVerified 4h ago

Job description

Job Description and Requirements Alternate Job TitlesEmbedded Memory Sr EngineerCMOS Memory Circuit Design Sr EngineerStaff Memory IP Design EngineerSRAM/ROM Compiler Sr EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not. You know how leakage, stability, and performance interact at the transistor level, and you have debugged enough layout-versus-schematic mismatches to spot a problem before it becomes a tape-out delay.You are comfortable moving between circuit simulation in SPICE, layout review with your physical design partners, and scripting in Perl or C-Shell to automate the repetitive parts so you can focus on the hard decisions. When a reliability issue surfaces late in a project, you do not panic. You pull the data, run the corners, talk to the foundry if needed, and find the root cause.Mentorship matters to you. You have learned that the best way to scale your impact is to help the engineer next to you get better, whether that means walking through a Monte Carlo setup or explaining why a particular design choice will not hold up under process variation. At Synopsys, you will work on memory IP that goes into chips used across automotive, mobile, AI, and data center applications.What You'll Be DoingDesign and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodesLead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validationSupervise and collaborate with layout engineers to ensure design intent is maintained through physical implementationWork with CAD and compiler teams to integrate memory designs into automated generation flows and verification environmentsDrive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologiesMentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principlesThe Impact You Will HaveDeliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing marketsImprove memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructureReduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologiesStrengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scaleSolve yield and reliability issues that directly affect customer tape-outs and production rampsEnable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges fasterWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File developmentDeep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modelingProficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verificationStrong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plusFluency in English and Vietnamese for technical communication and collaboration across global teamsWho You AreYou approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition aloneYou communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-makingYou take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeoutYou are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlinesYou collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effortThe Team You'll Be Part OfYou will join the embedded memory IP team in Ho Chi Minh City, a group focused on developing next-generation SRAM, ROM, and Register File compilers for advanced process nodes. The team works closely with Synopsys's global memory design community, foundry partners, and product engineering teams to deliver memory solutions that meet the performance, power, and area requirements of leading semiconductor companies.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesEmbedded Memory Sr EngineerCMOS Memory Circuit Design Sr EngineerStaff Memory IP Design EngineerSRAM/ROM Compiler Sr EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not. You know how leakage, stability, and performance interact at the transistor level, and you have debugged enough layout-versus-schematic mismatches to spot a problem before it becomes a tape-out delay.You are comfortable moving between circuit simulation in SPICE, layout review with your physical design partners, and scripting in Perl or C-Shell to automate the repetitive parts so you can focus on the hard decisions. When a reliability issue surfaces late in a project, you do not panic. You pull the data, run the corners, talk to the foundry if needed, and find the root cause.Mentorship matters to you. You have learned that the best way to scale your impact is to help the engineer next to you get better, whether that means walking through a Monte Carlo setup or explaining why a particular design choice will not hold up under process variation. At Synopsys, you will work on memory IP that goes into chips used across automotive, mobile, AI, and data center applications.What You'll Be DoingDesign and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodesLead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validationSupervise and collaborate with layout engineers to ensure design intent is maintained through physical implementationWork with CAD and compiler teams to integrate memory designs into automated generation flows and verification environmentsDrive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologiesMentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principlesThe Impact You Will HaveDeliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing marketsImprove memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructureReduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologiesStrengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scaleSolve yield and reliability issues that directly affect customer tape-outs and production rampsEnable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges fasterWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File developmentDeep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modelingProficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verificationStrong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plusFluency in English and Vietnamese for technical communication and collaboration across global teamsWho You AreYou approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition aloneYou communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-makingYou take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeoutYou are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlinesYou collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effortThe Team You'll Be Part OfYou will join the embedded memory IP team in Ho Chi Minh City, a group focused on developing next-generation SRAM, ROM, and Register File compilers for advanced process nodes. The team works closely with Synopsys's global memory design community, foundry partners, and product engineering teams to deliver memory solutions that meet the performance, power, and area requirements of leading semiconductor companies.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesEmbedded Memory Sr EngineerCMOS Memory Circuit Design Sr EngineerStaff Memory IP Design EngineerSRAM/ROM Compiler Sr EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not. You know how leakage, stability, and performance interact at the transistor level, and you have debugged enough layout-versus-schematic mismatches to spot a problem before it becomes a tape-out delay.You are comfortable moving between circuit simulation in SPICE, layout review with your physical design partners, and scripting in Perl or C-Shell to automate the repetitive parts so you can focus on the hard decisions. When a reliability issue surfaces late in a project, you do not panic. You pull the data, run the corners, talk to the foundry if needed, and find the root cause.Mentorship matters to you. You have learned that the best way to scale your impact is to help the engineer next to you get better, whether that means walking through a Monte Carlo setup or explaining why a particular design choice will not hold up under process variation. At Synopsys, you will work on memory IP that goes into chips used across automotive, mobile, AI, and data center applications.What You'll Be DoingDesign and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodesLead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validationSupervise and collaborate with layout engineers to ensure design intent is maintained through physical implementationWork with CAD and compiler teams to integrate memory designs into automated generation flows and verification environmentsDrive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologiesMentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principlesThe Impact You Will HaveDeliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing marketsImprove memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructureReduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologiesStrengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scaleSolve yield and reliability issues that directly affect customer tape-outs and production rampsEnable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges fasterWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File developmentDeep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modelingProficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verificationStrong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plusFluency in English and Vietnamese for technical communication and collaboration across global teamsWho You AreYou approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition aloneYou communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-makingYou take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeoutYou are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlinesYou collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effortThe Team You'll Be Part OfYou will join the embedded memory IP team in Ho Chi Minh City, a group focused on developing next-generation SRAM, ROM, and Register File compilers for advanced process nodes. The team works closely with Synopsys's global memory design community, foundry partners, and product engineering teams to deliver memory solutions that meet the performance, power, and area requirements of leading semiconductor companies.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Job Description and RequirementsAlternate Job TitlesEmbedded Memory Sr EngineerCMOS Memory Circuit Design Sr EngineerStaff Memory IP Design EngineerSRAM/ROM Compiler Sr EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not. You know how leakage, stability, and performance interact at the transistor level, and you have debugged enough layout-versus-schematic mismatches to spot a problem before it becomes a tape-out delay.You are comfortable moving between circuit simulation in SPICE, layout review with your physical design partners, and scripting in Perl or C-Shell to automate the repetitive parts so you can focus on the hard decisions. When a reliability issue surfaces late in a project, you do not panic. You pull the data, run the corners, talk to the foundry if needed, and find the root cause.Mentorship matters to you. You have learned that the best way to scale your impact is to help the engineer next to you get better, whether that means walking through a Monte Carlo setup or explaining why a particular design choice will not hold up under process variation. At Synopsys, you will work on memory IP that goes into chips used across automotive, mobile, AI, and data center applications.What You'll Be DoingDesign and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodesLead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validationSupervise and collaborate with layout engineers to ensure design intent is maintained through physical implementationWork with CAD and compiler teams to integrate memory designs into automated generation flows and verification environmentsDrive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologiesMentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principlesThe Impact You Will HaveDeliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing marketsImprove memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructureReduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologiesStrengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scaleSolve yield and reliability issues that directly affect customer tape-outs and production rampsEnable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges fasterWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File developmentDeep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modelingProficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verificationStrong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plusFluency in English and Vietnamese for technical communication and collaboration across global teamsWho You AreYou approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition aloneYou communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-makingYou take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeoutYou are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlinesYou collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effortThe Team You'll Be Part OfYou will join the embedded memory IP team in Ho Chi Minh City, a group focused on developing next-generation SRAM, ROM, and Register File compilers for advanced process nodes. The team works closely with Synopsys's global memory design community, foundry partners, and product engineering teams to deliver memory solutions that meet the performance, power, and area requirements of leading semiconductor companies.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles

Embedded Memory Sr Engineer

Embedded Memory Sr Engineer

CMOS Memory Circuit Design Sr Engineer

CMOS Memory Circuit Design Sr Engineer

Staff Memory IP Design Engineer

Staff Memory IP Design Engineer

SRAM/ROM Compiler Sr Engineer

SRAM/ROM Compiler Sr Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not. You know how leakage, stability, and performance interact at the transistor level, and you have debugged enough layout-versus-schematic mismatches to spot a problem before it becomes a tape-out delay.

You are comfortable moving between circuit simulation in SPICE, layout review with your physical design partners, and scripting in Perl or C-Shell to automate the repetitive parts so you can focus on the hard decisions. When a reliability issue surfaces late in a project, you do not panic. You pull the data, run the corners, talk to the foundry if needed, and find the root cause.

Mentorship matters to you. You have learned that the best way to scale your impact is to help the engineer next to you get better, whether that means walking through a Monte Carlo setup or explaining why a particular design choice will not hold up under process variation. At Synopsys, you will work on memory IP that goes into chips used across automotive, mobile, AI, and data center applications.

What You'll Be Doing

Design and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodes

Design and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodes

Lead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validation

Lead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validation

Supervise and collaborate with layout engineers to ensure design intent is maintained through physical implementation

Supervise and collaborate with layout engineers to ensure design intent is maintained through physical implementation

Work with CAD and compiler teams to integrate memory designs into automated generation flows and verification environments

Work with CAD and compiler teams to integrate memory designs into automated generation flows and verification environments

Drive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologies

Drive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologies

Mentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principles

Mentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principles

The Impact You Will Have

Deliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing markets

Deliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing markets

Improve memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructure

Improve memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructure

Reduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologies

Reduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologies

Strengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scale

Strengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scale

Solve yield and reliability issues that directly affect customer tape-outs and production ramps

Solve yield and reliability issues that directly affect customer tape-outs and production ramps

Enable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges faster

Enable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges faster

What You'll Need

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline

2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File development

2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File development

Deep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modeling

Deep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modeling

Proficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verification

Proficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verification

Strong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plus

Strong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plus

Fluency in English and Vietnamese for technical communication and collaboration across global teams

Fluency in English and Vietnamese for technical communication and collaboration across global teams

Who You Are

You approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition alone

You approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition alone

You communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-making

You communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-making

You take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeout

You take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeout

You are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlines

You are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlines

You collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effort

You collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effort

The Team You'll Be Part Of

You will join the embedded memory IP team in Ho Chi Minh City, a group focused on developing next-generation SRAM, ROM, and Register File compilers for advanced process nodes. The team works closely with Synopsys's global memory design community, foundry partners, and product engineering teams to deliver memory solutions that meet the performance, power, and area requirements of leading semiconductor companies.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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