Principal Silicon Engineer

Design and verify PLL cores for custom SerDes interface IP Architecture of the PLL core Review timing reports of critical timing cells inside the PLL core (e.g. digital loop filters & analog-to-digital timing interfaces) Simulation, post-layout verification & co-ordination with layout designers and other engineers on the macro Global clock distribution owner responsible for low jitter clocking for high-speed clocking spines across the SerDes macro Co-ordinate with modeling designers to ensure PLL functionality Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. 1+ year(s) experience working on or leading projects from beginning-to-end. 10+ years of experience in high-speed clocking and PLL design Experience with deep sub-micron nodes and hands on layout optimization experience Ability to review DV waveforms and debug calibration related issues Post silicon validation Python, Perl & other scripting languages for post silicon validation Matlab (Simulink) & modeling Analog Behavioural Modeling (ABM)