MTS - ESD Design Engineer

Req. ID: JR95955 MTS - ESD Design Engineer Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to ESD Architecture Leadership & Strategy Define and own ESD architecture and protection strategy for high-speed I/O portfolios including: * HBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os * PCIe, USB, Ethernet, MIPI, and proprietary interfaces * Lead ESD–I/O co‑design trade‑off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM).Ultra‑low capacitance and leakage requirements * Eye margin, jitter, bandwidth, return loss, and impedance matching * Drive architectural choices for: Snapback clamps, rail clamps, diode steering networks. Triggered and advanced ESD devices (technology‑dependent). Domain isolation and sequencing protection for sophisticated SoCs * Advanced Circuit Design, Modeling & Signoff: Perform and guide ESD circuit design and analysis at block and full‑chip level. * Establish simulation methodologies for: Transient ESD stress (TLP‑equivalent behavior). Dynamic clamp triggering and current handling. I/O performance impact (cap loading, ringing, overshoot/undershoot. * Own ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior). Drive correlation between SPICE simulations, TLP/VF‑TLP, and silicon results. Act as the final technical authority for ESD Design reviews and signoff. * Silicon Debug, Reliability & Qualification Ownership: Lead silicon-level ESD failure analysis across products and generations. * Drive root cause analysis for: HBM/CDM failures. Leakage and performance degradation. Latch‑up and substrate‑coupling issues * Collaborate deeply with reliability: Define corrective actions and preventive methodologies. Own ESD qualification strategies and ensure first‑pass silicon success. * Physical Design, Layout & Technology Engagement: Define company-wide layout guidelines for ESD devices. Current uniformity, ballasting, guard rings. Substrate/well engineering and isolation standard processes. Power clamp placement and return path integrity * Partner with technology, process, and PDK teams to: Influence ESD-friendly process features. Enable scalable ESD solutions in sophisticated node & Ensure ESD robustness across multiple packages and IO ring configurations. * Multi-functional & Interpersonal Leadership: Serve as the ESD subject-matter guide (SME) across the organization. * Provide strategic guidance to: I/O and PHY design teams. PDN, package, and board-level engineers. Product engineering and manufacturing. Mentor and technically develop junior and senior ESD/design engineers & Drive methodology reuse, IP standardization, and design standard processes across programs. * Consistent track record of: Delivering production silicon meeting aggressive ESD and performance targets. Leading ESD technical decisions for sophisticated, high‑volume products. * Deep expertise in: HBM, CDM, MM, latch‑up mechanisms & High-speed signal integrity fundamentals and constraints * Strong command of: SPICE-based simulators (Spectre, HSPICE) & Physical layout review and ESD signoff flows * Leadership & Soft Skills: Recognized technical authority with strong executive‑level interpersonal skills. Ability to make and defend data‑driven architectural trade‑offs. Mentor‑first attitude with passion for growing technical talent. Comfort operating in ambiguous, fast‑paced, first‑principles problem spaces. ## What Success Looks Like * ESD requirements consistently met without compromising high-speed I/O performance. * Predictable, silicon‑correlated ESD signoff across projects. * Reusable ESD IP and methodologies deployed across multiple products and nodes. ## Requirements/Qualification * B.Tech / M.Tech / PhD in Electrical / Electronic Engineering or related team. * 15+ years of hands‑on experience in: ESD circuit design and protection architecture& High-speed I/O or mixed-signal chip environments Department Intro... A few sentences about the department here. Job Profile(s): Semiconductor Design Eng MTS Relocation level: (TBD) Before Getting Started Please review Micron’s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that: * Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence. * If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process. ​​​​ As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.