Job description
Layout Engineer
Job Description: RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area. Qualifications: - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command of Japanese. - Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Job Description: RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area. Qualifications: - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command of Japanese. - Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Job Description: RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area. Qualifications: - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command of Japanese. - Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Job Description: RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area. Qualifications: - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command of Japanese. - Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Job Description: RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area. Qualifications: - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command of Japanese. - Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Job Description: RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area. Qualifications: - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device background will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command of Japanese. - Be able to communicate with customer in English is a plus. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
Job Description:
RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area.