Layout Design, Sr Engineer in Da Nang

Job Description and Requirements Alternate Job TitlesCustom Layout EngineerIC Layout DesignerVLSI Layout EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.You are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.At Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.What You'll Be DoingDesign custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targetsRun and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root causeAnalyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirementsCollaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goalsBuild and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistencySupport bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validationThe Impact You Will HaveDeliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor marketsImprove silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respinsAccelerate project schedules by automating layout tasks and verification flowsRaise the bar for layout quality across the team by sharing best practices and debugging techniquesEnable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teamsHelp define layout methodologies that scale across multiple process nodes and design familiesWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field2+ years of hands-on experience in custom layout, standard cell layout, or memory layout designStrong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysisProficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platformsSolid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist sourceWho You AreYou approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisionsYou do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needsYou are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentumYou communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffsThe Team You'll Be Part OfYou will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesCustom Layout EngineerIC Layout DesignerVLSI Layout EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.You are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.At Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.What You'll Be DoingDesign custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targetsRun and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root causeAnalyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirementsCollaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goalsBuild and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistencySupport bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validationThe Impact You Will HaveDeliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor marketsImprove silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respinsAccelerate project schedules by automating layout tasks and verification flowsRaise the bar for layout quality across the team by sharing best practices and debugging techniquesEnable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teamsHelp define layout methodologies that scale across multiple process nodes and design familiesWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field2+ years of hands-on experience in custom layout, standard cell layout, or memory layout designStrong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysisProficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platformsSolid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist sourceWho You AreYou approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisionsYou do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needsYou are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentumYou communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffsThe Team You'll Be Part OfYou will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesCustom Layout EngineerIC Layout DesignerVLSI Layout EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.You are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.At Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.What You'll Be DoingDesign custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targetsRun and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root causeAnalyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirementsCollaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goalsBuild and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistencySupport bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validationThe Impact You Will HaveDeliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor marketsImprove silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respinsAccelerate project schedules by automating layout tasks and verification flowsRaise the bar for layout quality across the team by sharing best practices and debugging techniquesEnable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teamsHelp define layout methodologies that scale across multiple process nodes and design familiesWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field2+ years of hands-on experience in custom layout, standard cell layout, or memory layout designStrong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysisProficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platformsSolid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist sourceWho You AreYou approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisionsYou do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needsYou are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentumYou communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffsThe Team You'll Be Part OfYou will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Job Description and RequirementsAlternate Job TitlesCustom Layout EngineerIC Layout DesignerVLSI Layout EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.You are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.At Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.What You'll Be DoingDesign custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targetsRun and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root causeAnalyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirementsCollaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goalsBuild and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistencySupport bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validationThe Impact You Will HaveDeliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor marketsImprove silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respinsAccelerate project schedules by automating layout tasks and verification flowsRaise the bar for layout quality across the team by sharing best practices and debugging techniquesEnable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teamsHelp define layout methodologies that scale across multiple process nodes and design familiesWhat You'll NeedBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field2+ years of hands-on experience in custom layout, standard cell layout, or memory layout designStrong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysisProficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platformsSolid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist sourceWho You AreYou approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisionsYou do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needsYou are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentumYou communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffsThe Team You'll Be Part OfYou will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Alternate Job Titles

• Custom Layout Engineer
• IC Layout Designer
• VLSI Layout Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.

You are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.

At Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.

What You'll Be Doing

• Design custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targets
• Run and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root cause
• Analyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirements
• Collaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goals
• Build and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistency
• Support bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validation

The Impact You Will Have

• Deliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor markets
• Improve silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respins
• Accelerate project schedules by automating layout tasks and verification flows
• Raise the bar for layout quality across the team by sharing best practices and debugging techniques
• Enable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teams
• Help define layout methodologies that scale across multiple process nodes and design families

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• 2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design
• Strong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysis
• Proficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platforms
• Solid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist source

Who You Are

• You approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisions
• You do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needs
• You are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentum
• You communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffs

The Team You'll Be Part Of

You will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

• Back to job list

Back to job listApplyApplyApplyApplyApply