Digital Verification Senior Staff Engineer

Job Description and Requirements Alternate Job TitlesDigital Verification Senior Staff EngineerMixed-Signal PHY Verification LeadASIC Verification Sr Staff EngineerRTL/GLS Verification Senior Staff EngineerHigh-Speed Interface Verification Senior Staff EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.What You'll Be DoingDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteriaPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environmentsBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocksGenerate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumptionDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causesCollaborate with design, analog, and integration teams to align verification strategy with IP architectureReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close themThe Impact You Will HaveCatch critical bugs before tapeout, preventing costly respins and protecting customer schedulesEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocksImprove verification quality across the team by building reusable test components and coverage modelsProvide early feedback to design teams on corner cases, timing issues, and power anomaliesSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage rangesStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIeReduce post-silicon debug cycles by catching gate-level and power issues during simulationWhat You'll Need5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debuggingDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLSProficiency in SystemVerilog and experience working within UVM-based verification environmentsStrong debugging skills across waveform analysis, coverage review, and simulation log interpretationExperience with power analysis tools such as PrimeTime PX, including VCD generationKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plusBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experienceWho You AreYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slidesYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gapsYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precisionYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixesYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussionsThe Team You'll Be Part OfYou will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesDigital Verification Senior Staff EngineerMixed-Signal PHY Verification LeadASIC Verification Sr Staff EngineerRTL/GLS Verification Senior Staff EngineerHigh-Speed Interface Verification Senior Staff EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.What You'll Be DoingDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteriaPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environmentsBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocksGenerate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumptionDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causesCollaborate with design, analog, and integration teams to align verification strategy with IP architectureReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close themThe Impact You Will HaveCatch critical bugs before tapeout, preventing costly respins and protecting customer schedulesEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocksImprove verification quality across the team by building reusable test components and coverage modelsProvide early feedback to design teams on corner cases, timing issues, and power anomaliesSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage rangesStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIeReduce post-silicon debug cycles by catching gate-level and power issues during simulationWhat You'll Need5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debuggingDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLSProficiency in SystemVerilog and experience working within UVM-based verification environmentsStrong debugging skills across waveform analysis, coverage review, and simulation log interpretationExperience with power analysis tools such as PrimeTime PX, including VCD generationKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plusBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experienceWho You AreYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slidesYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gapsYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precisionYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixesYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussionsThe Team You'll Be Part OfYou will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesDigital Verification Senior Staff EngineerMixed-Signal PHY Verification LeadASIC Verification Sr Staff EngineerRTL/GLS Verification Senior Staff EngineerHigh-Speed Interface Verification Senior Staff EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.What You'll Be DoingDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteriaPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environmentsBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocksGenerate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumptionDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causesCollaborate with design, analog, and integration teams to align verification strategy with IP architectureReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close themThe Impact You Will HaveCatch critical bugs before tapeout, preventing costly respins and protecting customer schedulesEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocksImprove verification quality across the team by building reusable test components and coverage modelsProvide early feedback to design teams on corner cases, timing issues, and power anomaliesSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage rangesStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIeReduce post-silicon debug cycles by catching gate-level and power issues during simulationWhat You'll Need5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debuggingDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLSProficiency in SystemVerilog and experience working within UVM-based verification environmentsStrong debugging skills across waveform analysis, coverage review, and simulation log interpretationExperience with power analysis tools such as PrimeTime PX, including VCD generationKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plusBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experienceWho You AreYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slidesYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gapsYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precisionYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixesYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussionsThe Team You'll Be Part OfYou will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Job Description and RequirementsAlternate Job TitlesDigital Verification Senior Staff EngineerMixed-Signal PHY Verification LeadASIC Verification Sr Staff EngineerRTL/GLS Verification Senior Staff EngineerHigh-Speed Interface Verification Senior Staff EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.What You'll Be DoingDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteriaPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environmentsBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocksGenerate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumptionDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causesCollaborate with design, analog, and integration teams to align verification strategy with IP architectureReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close themThe Impact You Will HaveCatch critical bugs before tapeout, preventing costly respins and protecting customer schedulesEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocksImprove verification quality across the team by building reusable test components and coverage modelsProvide early feedback to design teams on corner cases, timing issues, and power anomaliesSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage rangesStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIeReduce post-silicon debug cycles by catching gate-level and power issues during simulationWhat You'll Need5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debuggingDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLSProficiency in SystemVerilog and experience working within UVM-based verification environmentsStrong debugging skills across waveform analysis, coverage review, and simulation log interpretationExperience with power analysis tools such as PrimeTime PX, including VCD generationKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plusBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experienceWho You AreYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slidesYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gapsYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precisionYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixesYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussionsThe Team You'll Be Part OfYou will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Alternate Job TitlesDigital Verification Senior Staff EngineerMixed-Signal PHY Verification LeadASIC Verification Sr Staff EngineerRTL/GLS Verification Senior Staff EngineerHigh-Speed Interface Verification Senior Staff EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.What You'll Be DoingDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteriaPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environmentsBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocksGenerate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumptionDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causesCollaborate with design, analog, and integration teams to align verification strategy with IP architectureReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close themThe Impact You Will HaveCatch critical bugs before tapeout, preventing costly respins and protecting customer schedules

Alternate Job Titles

Alternate Job TitlesAlternate Job Titles

• Digital Verification Senior Staff Engineer

Digital Verification Senior Staff EngineerDigital Verification Senior StaffEngineer

• Mixed-Signal PHY Verification Lead

Mixed-Signal PHY Verification LeadMixed-Signal PHY Verification Lead

• ASIC Verification Sr Staff Engineer

ASIC Verification Sr Staff EngineerASIC Verification Sr Staff Engineer

• RTL/GLS Verification Senior Staff Engineer

RTL/GLS Verification Senior Staff EngineerRTL/GLS Verification Senior StaffEngineer

• High-Speed Interface Verification Senior Staff Engineer

High-Speed Interface Verification Senior Staff EngineerHigh-Speed Interface Verification Senior StaffEngineer

We Are

We AreWe Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You AreYou Are

You have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.

You have spent years in the verification trenches where the difference between a clean tapeout and a respin comes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you are actually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generation compute.You have spent years in the verification trenches where the difference between a cleantapeoutand arespincomes down to the corner case you caught at 2am. Simulation results don't lie, and you have learned to read between the waveforms to find what's actually broken versus what just looks wrong. Mixed-signal PHY work excites you because it sits at the hardest intersection: digital logic meeting analog reality, high-speed interfaces where timing is measured in picoseconds, and power constraints that make every toggle count. You operate comfortably in UVM environments, but you also know when to step outside the framework and write the directed test that actually stresses the thing everyone is worried about. Verification plans are living documents for you, not checkboxes. Working across RTL and GLS doesn't feel like two different jobs. It's a continuum, and you know how to move between abstraction levels without losing sight of what you areactually verifying. At Synopsys, you will work on PHY IP that powers the memory and interconnect infrastructure inside chips that run AI, data centers, and next-generationcompute.

What You'll Be Doing

What You'll Be DoingWhat You'll Be Doing

• Develop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteria

Develop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteriaDevelop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteria

• Perform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environments

Perform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environmentsPerform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environments

• Build functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocks

Build functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocksBuild functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocks

• Generate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumption

Generate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumptionGenerate VCD files and run power analysis usingPrimeTimePX, correlating simulation activity with power consumption

• Debug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes

Debug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causesDebug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes

• Collaborate with design, analog, and integration teams to align verification strategy with IP architecture

Collaborate with design, analog, and integration teams to align verification strategy with IP architectureCollaborate with design, analog, and integration teams to align verification strategy with IP architecture

• Review and refine verification infrastructure, identifying coverage gaps and proposing new tests to close them

Review and refine verification infrastructure, identifying coverage gaps and proposing new tests to close themReview and refine verification infrastructure, identifying coverage gaps and proposing new tests to close them

The Impact You Will Have

The Impact You Will HaveThe Impact You Will Have

• Catch critical bugs before tapeout, preventing costly respins and protecting customer schedules

Catch critical bugs before tapeout, preventing costly respins and protecting customer schedulesCatch critical bugs beforetapeout, preventing costlyrespinsand protecting customer schedulesEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocksImprove verification quality across the team by building reusable test components and coverage modelsProvide early feedback to design teams on corner cases, timing issues, and power anomaliesSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage rangesStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIeReduce post-silicon debug cycles by catching gate-level and power issues during simulationWhat You'll Need5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debuggingDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLSProficiency in SystemVerilog and experience working within UVM-based verification environmentsStrong debugging skills across waveform analysis, coverage review, and simulation log interpretationExperience with power analysis tools such as PrimeTime PX, including VCD generationKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plusBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experienceWho You AreYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slidesYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gapsYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precisionYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixesYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussions

• Enable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocks

Enable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocksEnable faster time-to-market for Synopsys PHY IP by delivering verified, production-ready blocks

• Improve verification quality across the team by building reusable test components and coverage models

Improve verification quality across the team by building reusable test components and coverage modelsImprove verification quality across the team by building reusable test components and coverage models

• Provide early feedback to design teams on corner cases, timing issues, and power anomalies

Provide early feedback to design teams on corner cases, timing issues, and power anomaliesProvide early feedback to design teams on corner cases, timing issues, and power anomalies

• Support successful customer integrations by ensuring PHY IP works reliably across process corners and voltage ranges

Support successful customer integrations by ensuring PHY IP works reliably across process corners and voltage rangesSupport successful customer integrations by ensuring PHY IP works reliably across process corners and voltage ranges

• Strengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIe

Strengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIeStrengthen the verification foundation for next-generation PHY products including DDR, HBM, and UCIe

• Reduce post-silicon debug cycles by catching gate-level and power issues during simulation

Reduce post-silicon debug cycles by catching gate-level and power issues during simulationReduce post-silicon debug cycles by catching gate-level and power issues during simulation

What You'll Need

What You'll NeedWhat You'll Need

• 5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debugging

5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debugging5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debugging

• Demonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLS

Demonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLSDemonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLS

• Proficiency in SystemVerilog and experience working within UVM-based verification environments

Proficiency in SystemVerilog and experience working within UVM-based verification environmentsProficiency inSystemVerilogand experience working within UVM-based verification environments

• Strong debugging skills across waveform analysis, coverage review, and simulation log interpretation

Strong debugging skills across waveform analysis, coverage review, and simulation log interpretationStrong debugging skills across waveform analysis, coverage review, and simulation log interpretation

• Experience with power analysis tools such as PrimeTime PX, including VCD generation

Experience with power analysis tools such as PrimeTime PX, including VCD generationExperience with power analysis tools such asPrimeTimePX, including VCD generation

• Knowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plus

Knowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plusKnowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plus

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experienceBachelor's orMaster's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience

Who You Are

Who You AreWho You Are

• You can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slides

You can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slidesYou can look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slides

• You treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gaps

You treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gapsYou treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gaps

• You communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precision

You communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precisionYou communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precision

• You stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixes

You stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixesYou stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixes

• You are comfortable working in English across global teams, writing clear bug reports and participating in technical discussions

You are comfortable working in English across global teams, writing clear bug reports and participating in technical discussionsYou are comfortable working in English across global teams, writing clear bug reports and participating in technical discussions

The Team You'll Be Part Of

The Team You'll Be Part OfThe Team You'll Be Part Of

You will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.

You will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.You will join a Digital Design team focused on developing high-speed mixed-signal PHY IP that powers memory interfaces and interconnects in advanced semiconductor products. The team works across RTL design, verification, and integration, collaborating closely with analog designers, architecture teams, and customer-facing engineers to deliver production-ready IP blocks.

Rewards and Benefits

Rewards and BenefitsRewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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