Digital Verification Engineer

Nexthop AILocation: Santa Clara, CAfull time

Activeverified Jul 30, 2026

Job description

Privacy Policy{"@context":"http://schema.org","@type":"JobPosting","title":"Digital Verification Engineer","description":"

Digital Verification Engineer<\/span><\/p>\n

Location: Santa Clara, CA<\/span><\/p>\n

Ladder: Silicon / Hardware Design<\/span><\/p>\n

Travel: Minimal (0–10%)<\/span><\/p>\n

Role Overview<\/span><\/p>\n

At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.<\/span><\/p>\n

Key Responsibilities<\/span><\/p>\n

1. Verification Environment Ownership<\/span><\/p>\n

Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.<\/span><\/li>\n
Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.<\/span><\/li>\n
Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.<\/span><\/li>\n<\/ul>\n
2. Test Development & Coverage<\/span><\/p>\n
- Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.<\/span><\/li>\n
- Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.<\/span><\/li>\n
- Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.<\/span><\/li>\n<\/ul>\n
  3. Simulation, Debug & Regression<\/span><\/p>\n
  - Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.<\/span><\/li>\n
  - Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.<\/span><\/li>\n
  - Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop.<\/span><\/li>\n<\/ul>\n
    4. System Bring-up & HW/SW Co-validation<\/span><\/p>\n
    - Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.<\/span><\/li>\n
    - Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.<\/span><\/li>\n
    - Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.<\/span><\/li>\n<\/ul>\n
      Required Qualifications<\/span><\/p>\n
      - Experience: 3–7 years of digital verification experience on FPGA or ASIC designs.<\/span><\/li>\n
      - Language: Proficiency in Verilog (SystemVerilog strongly preferred).<\/span><\/li>\n
      - Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog.<\/span><\/li>\n
      - Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions.<\/span><\/li>\n
      - Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.<\/span><\/li>\n<\/ul>\n
        Strong Pluses<\/span><\/p>\n
        \n
        Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).<\/span><\/li>\n
        Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.<\/span><\/li>\n
        Structured verification methodology experience (UVM or equivalent).<\/span><\/li>\n
        Familiarity with networking / switching datapaths or high-speed interfaces.<\/span><\/li>\n<\/ul>\n
        What Success Looks Like<\/span><\/p>\n
        \n
        Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.<\/span><\/li>\n
        Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on \"it seems to work.\"<\/span><\/li>\n
        A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence.<\/span><\/li>\n
        Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.<\/span><\/li>\n<\/ul>","identifier":{"@type":"PropertyValue","name":"Nexthop Systems Inc","value":"100"},"datePosted":"2026-07-22","employmentType":"OTHER","hiringOrganization":{"@type":"Organization","name":"Nexthop Systems Inc","logo":"https://images7.bamboohr.com/652331/logos/cropped.jpg?v=37"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"California","postalCode":"95054","addressCountry":"United States"}},"url":"https://nexthopai.bamboohr.com/careers/100"}Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting. Apply for This JobLink to This JobLocationSanta Clara, California (Hybrid)Department3110 - Engr HWEmployment TypeFull-TimePrivacy Policy • Terms of Service • © BambooHR All rights reserved.
        Privacy Policy{"@context":"http://schema.org","@type":"JobPosting","title":"Digital Verification Engineer","description":"
        Digital Verification Engineer<\/span><\/p>\n
        Location: Santa Clara, CA<\/span><\/p>\n
        Ladder: Silicon / Hardware Design<\/span><\/p>\n
        Travel: Minimal (0–10%)<\/span><\/p>\n
        Role Overview<\/span><\/p>\n
        At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.<\/span><\/p>\n
        Key Responsibilities<\/span><\/p>\n
        1. Verification Environment Ownership<\/span><\/p>\n
        \n
        Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.<\/span><\/li>\n
        Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.<\/span><\/li>\n
        Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.<\/span><\/li>\n<\/ul>\n
        2. Test Development & Coverage<\/span><\/p>\n
        \n
        Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.<\/span><\/li>\n
        Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.<\/span><\/li>\n
        Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.<\/span><\/li>\n<\/ul>\n
        3. Simulation, Debug & Regression<\/span><\/p>\n
        \n
        Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.<\/span><\/li>\n
        Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.<\/span><\/li>\n
        Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop.<\/span><\/li>\n<\/ul>\n
        4. System Bring-up & HW/SW Co-validation<\/span><\/p>\n
        \n
        Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.<\/span><\/li>\n
        Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.<\/span><\/li>\n
        Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.<\/span><\/li>\n<\/ul>\n
        Required Qualifications<\/span><\/p>\n
        \n
        Experience: 3–7 years of digital verification experience on FPGA or ASIC designs.<\/span><\/li>\n
        Language: Proficiency in Verilog (SystemVerilog strongly preferred).<\/span><\/li>\n
        Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog.<\/span><\/li>\n
        Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions.<\/span><\/li>\n
        Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.<\/span><\/li>\n<\/ul>\n
        Strong Pluses<\/span><\/p>\n
        \n
        Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).<\/span><\/li>\n
        Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.<\/span><\/li>\n
        Structured verification methodology experience (UVM or equivalent).<\/span><\/li>\n
        Familiarity with networking / switching datapaths or high-speed interfaces.<\/span><\/li>\n<\/ul>\n
        What Success Looks Like<\/span><\/p>\n
        \n
        Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.<\/span><\/li>\n
        Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on \"it seems to work.\"<\/span><\/li>\n
        A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence.<\/span><\/li>\n
        Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.<\/span><\/li>\n<\/ul>","identifier":{"@type":"PropertyValue","name":"Nexthop Systems Inc","value":"100"},"datePosted":"2026-07-22","employmentType":"OTHER","hiringOrganization":{"@type":"Organization","name":"Nexthop Systems Inc","logo":"https://images7.bamboohr.com/652331/logos/cropped.jpg?v=37"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"California","postalCode":"95054","addressCountry":"United States"}},"url":"https://nexthopai.bamboohr.com/careers/100"}Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting. Apply for This JobLink to This JobLocationSanta Clara, California (Hybrid)Department3110 - Engr HWEmployment TypeFull-TimePrivacy Policy • Terms of Service • © BambooHR All rights reserved.
        Privacy Policy{"@context":"http://schema.org","@type":"JobPosting","title":"Digital Verification Engineer","description":"
        Digital Verification Engineer<\/span><\/p>\n
        Location: Santa Clara, CA<\/span><\/p>\n
        Ladder: Silicon / Hardware Design<\/span><\/p>\n
        Travel: Minimal (0–10%)<\/span><\/p>\n
        Role Overview<\/span><\/p>\n
        At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.<\/span><\/p>\n
        Key Responsibilities<\/span><\/p>\n
        1. Verification Environment Ownership<\/span><\/p>\n
        \n
        Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.<\/span><\/li>\n
        Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.<\/span><\/li>\n
        Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.<\/span><\/li>\n<\/ul>\n
        2. Test Development & Coverage<\/span><\/p>\n
        \n
        Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.<\/span><\/li>\n
        Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.<\/span><\/li>\n
        Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.<\/span><\/li>\n<\/ul>\n
        3. Simulation, Debug & Regression<\/span><\/p>\n
        \n
        Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.<\/span><\/li>\n
        Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.<\/span><\/li>\n
        Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop.<\/span><\/li>\n<\/ul>\n
        4. System Bring-up & HW/SW Co-validation<\/span><\/p>\n
        \n
        Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.<\/span><\/li>\n
        Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.<\/span><\/li>\n
        Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.<\/span><\/li>\n<\/ul>\n
        Required Qualifications<\/span><\/p>\n
        \n
        Experience: 3–7 years of digital verification experience on FPGA or ASIC designs.<\/span><\/li>\n
        Language: Proficiency in Verilog (SystemVerilog strongly preferred).<\/span><\/li>\n
        Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog.<\/span><\/li>\n
        Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions.<\/span><\/li>\n
        Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.<\/span><\/li>\n<\/ul>\n
        Strong Pluses<\/span><\/p>\n
        \n
        Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).<\/span><\/li>\n
        Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.<\/span><\/li>\n
        Structured verification methodology experience (UVM or equivalent).<\/span><\/li>\n
        Familiarity with networking / switching datapaths or high-speed interfaces.<\/span><\/li>\n<\/ul>\n
        What Success Looks Like<\/span><\/p>\n
        \n
        Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.<\/span><\/li>\n
        Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on \"it seems to work.\"<\/span><\/li>\n
        A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence.<\/span><\/li>\n
        Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.<\/span><\/li>\n<\/ul>","identifier":{"@type":"PropertyValue","name":"Nexthop Systems Inc","value":"100"},"datePosted":"2026-07-22","employmentType":"OTHER","hiringOrganization":{"@type":"Organization","name":"Nexthop Systems Inc","logo":"https://images7.bamboohr.com/652331/logos/cropped.jpg?v=37"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"California","postalCode":"95054","addressCountry":"United States"}},"url":"https://nexthopai.bamboohr.com/careers/100"}Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting. Apply for This JobLink to This JobLocationSanta Clara, California (Hybrid)Department3110 - Engr HWEmployment TypeFull-TimePrivacy Policy • Terms of Service • © BambooHR All rights reserved.
        Privacy Policy{"@context":"http://schema.org","@type":"JobPosting","title":"Digital Verification Engineer","description":"
        Digital Verification Engineer<\/span><\/p>\n
        Location: Santa Clara, CA<\/span><\/p>\n
        Ladder: Silicon / Hardware Design<\/span><\/p>\n
        Travel: Minimal (0–10%)<\/span><\/p>\n
        Role Overview<\/span><\/p>\n
        At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.<\/span><\/p>\n
        Key Responsibilities<\/span><\/p>\n
        1. Verification Environment Ownership<\/span><\/p>\n
        \n
        Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.<\/span><\/li>\n
        Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.<\/span><\/li>\n
        Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.<\/span><\/li>\n<\/ul>\n
        2. Test Development & Coverage<\/span><\/p>\n
        \n
        Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.<\/span><\/li>\n
        Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.<\/span><\/li>\n
        Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.<\/span><\/li>\n<\/ul>\n
        3. Simulation, Debug & Regression<\/span><\/p>\n
        \n
        Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.<\/span><\/li>\n
        Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.<\/span><\/li>\n
        Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop.<\/span><\/li>\n<\/ul>\n
        4. System Bring-up & HW/SW Co-validation<\/span><\/p>\n
        \n
        Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.<\/span><\/li>\n
        Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.<\/span><\/li>\n
        Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.<\/span><\/li>\n<\/ul>\n
        Required Qualifications<\/span><\/p>\n
        \n
        Experience: 3–7 years of digital verification experience on FPGA or ASIC designs.<\/span><\/li>\n
        Language: Proficiency in Verilog (SystemVerilog strongly preferred).<\/span><\/li>\n
        Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog.<\/span><\/li>\n
        Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions.<\/span><\/li>\n
        Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.<\/span><\/li>\n<\/ul>\n
        Strong Pluses<\/span><\/p>\n
        \n
        Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).<\/span><\/li>\n
        Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.<\/span><\/li>\n
        Structured verification methodology experience (UVM or equivalent).<\/span><\/li>\n
        Familiarity with networking / switching datapaths or high-speed interfaces.<\/span><\/li>\n<\/ul>\n
        What Success Looks Like<\/span><\/p>\n
        \n
        Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.<\/span><\/li>\n
        Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on \"it seems to work.\"<\/span><\/li>\n
        A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence.<\/span><\/li>\n
        Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.<\/span><\/li>\n<\/ul>","identifier":{"@type":"PropertyValue","name":"Nexthop Systems Inc","value":"100"},"datePosted":"2026-07-22","employmentType":"OTHER","hiringOrganization":{"@type":"Organization","name":"Nexthop Systems Inc","logo":"https://images7.bamboohr.com/652331/logos/cropped.jpg?v=37"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"California","postalCode":"95054","addressCountry":"United States"}},"url":"https://nexthopai.bamboohr.com/careers/100"}Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting. Apply for This JobLink to This JobLocationSanta Clara, California (Hybrid)Department3110 - Engr HWEmployment TypeFull-TimePrivacy Policy • Terms of Service • © BambooHR All rights reserved.
        Privacy Policy{"@context":"http://schema.org","@type":"JobPosting","title":"Digital Verification Engineer","description":"
        Digital Verification Engineer<\/span><\/p>\n
        Location: Santa Clara, CA<\/span><\/p>\n
        Ladder: Silicon / Hardware Design<\/span><\/p>\n
        Travel: Minimal (0–10%)<\/span><\/p>\n
        Role Overview<\/span><\/p>\n
        At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.<\/span><\/p>\n
        Key Responsibilities<\/span><\/p>\n
        1. Verification Environment Ownership<\/span><\/p>\n
        \n
        Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.<\/span><\/li>\n
        Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.<\/span><\/li>\n
        Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.<\/span><\/li>\n<\/ul>\n
        2. Test Development & Coverage<\/span><\/p>\n
        \n
        Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.<\/span><\/li>\n
        Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.<\/span><\/li>\n
        Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.<\/span><\/li>\n<\/ul>\n
        3. Simulation, Debug & Regression<\/span><\/p>\n
        \n
        Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.<\/span><\/li>\n
        Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.<\/span><\/li>\n
        Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop.<\/span><\/li>\n<\/ul>\n
        4. System Bring-up & HW/SW Co-validation<\/span><\/p>\n
        \n
        Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.<\/span><\/li>\n
        Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.<\/span><\/li>\n
        Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.<\/span><\/li>\n<\/ul>\n
        Required Qualifications<\/span><\/p>\n
        \n
        Experience: 3–7 years of digital verification experience on FPGA or ASIC designs.<\/span><\/li>\n
        Language: Proficiency in Verilog (SystemVerilog strongly preferred).<\/span><\/li>\n
        Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog.<\/span><\/li>\n
        Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions.<\/span><\/li>\n
        Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.<\/span><\/li>\n<\/ul>\n
        Strong Pluses<\/span><\/p>\n
        \n
        Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).<\/span><\/li>\n
        Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.<\/span><\/li>\n
        Structured verification methodology experience (UVM or equivalent).<\/span><\/li>\n
        Familiarity with networking / switching datapaths or high-speed interfaces.<\/span><\/li>\n<\/ul>\n
        What Success Looks Like<\/span><\/p>\n
        \n
        Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.<\/span><\/li>\n
        Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on \"it seems to work.\"<\/span><\/li>\n
        A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence.<\/span><\/li>\n
        Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.<\/span><\/li>\n<\/ul>","identifier":{"@type":"PropertyValue","name":"Nexthop Systems Inc","value":"100"},"datePosted":"2026-07-22","employmentType":"OTHER","hiringOrganization":{"@type":"Organization","name":"Nexthop Systems Inc","logo":"https://images7.bamboohr.com/652331/logos/cropped.jpg?v=37"},"jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Santa Clara","addressRegion":"California","postalCode":"95054","addressCountry":"United States"}},"url":"https://nexthopai.bamboohr.com/careers/100"}Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting. Apply for This JobLink to This JobLocationSanta Clara, California (Hybrid)Department3110 - Engr HWEmployment TypeFull-Time
        Privacy Policy
        Privacy Policy
        Privacy Policy
        Privacy Policy
        Privacy Policy
        Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting. Apply for This JobLink to This JobLocationSanta Clara, California (Hybrid)Department3110 - Engr HWEmployment TypeFull-Time
        Job OpeningsDigital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.
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        Digital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)
        Digital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)
        Digital Verification Engineer3110 - Engr HW - Santa Clara, California (Hybrid)
        Digital Verification Engineer
        3110 - Engr HW - Santa Clara, California (Hybrid)
        Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.
        Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.
        Digital Verification Engineer Location: Santa Clara, CA Ladder: Silicon / Hardware Design Travel: Minimal (0–10%) Role Overview At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack. Key Responsibilities 1. Verification Environment Ownership Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets. Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them. Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. Regression: Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop. 4. System Bring-up & HW/SW Co-validation Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. Software collaboration: Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. Required Qualifications Experience: 3–7 years of digital verification experience on FPGA or ASIC designs. Language: Proficiency in Verilog (SystemVerilog strongly preferred). Tools: Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog. Methodology: Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions. Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. Structured verification methodology experience (UVM or equivalent). Familiarity with networking / switching datapaths or high-speed interfaces. What Success Looks Like Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them. Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage — no block signs off on "it seems to work." A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence. Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly — no late-stage firefighting.
        Digital Verification Engineer
        Digital Verification Engineer
        Location: Santa Clara, CA
        Location: Santa Clara, CA
        Ladder: Silicon / Hardware Design
        Ladder: Silicon / Hardware Design
        Travel: Minimal (0–10%)
        Travel: Minimal (0–10%)
        Role Overview
        Role Overview
        At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.
        At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.
        Key Responsibilities
        Key Responsibilities
        1. Verification Environment Ownership
        1. Verification Environment Ownership
        Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.
        Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.
        Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.
        Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.
        Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.
        Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.
        2. Test Development & Coverage
        2. Test Development & Coverage
        Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.
        Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.
        Coverage-driven closure: Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.