DFT Engineer (Yokohama or Osaka, 14, JP)

DFT Engineer

Job Description • Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery ■Qualification • BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must" All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Job Description • Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery ■Qualification • BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must" All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Job Description • Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery ■Qualification • BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must" All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Job Description • Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery ■Qualification • BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must" All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Job Description • Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery ■Qualification • BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must" All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Job Description • Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery ■Qualification • BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must" All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Job Description

• Defect modeling and test methodology development for advanced process nodes, advanced packaging technologies • Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation • Verify DFT circuitry and interface with other blocks, debug timing simulation issues • Closely work with physical design team to resolve timing constraints/issues • Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning • Work independently and own the task from DFT specification to final pattern delivery

■Qualification

• BCH and above in EE, CS related fields. • 3-15 years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with Tessent and Modus/Encounter tool suite is a plus • Strong programming skills in Python/TCL and shell scripting is required • Proficiency in English is a must"

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.

Date: Aug 2, 2026

Date: Aug 2, 2026

Date: Aug 2, 2026

Date: Aug 2, 2026

Date:

Aug 2, 2026

Country/Region: JP

Country/Region: JP

Country/Region: JP

Country/Region: JP

Country/Region:

JP

City: Yokohama or Osaka

City: Yokohama or Osaka

City: Yokohama or Osaka

City: Yokohama or Osaka

City:

Yokohama or Osaka

Company: TSMC Design Tech. Japan, Inc.

Company: TSMC Design Tech. Japan, Inc.

Company: TSMC Design Tech. Japan, Inc.

Company: TSMC Design Tech. Japan, Inc.

Company:

TSMC Design Tech. Japan, Inc.