Design Verification Sr Engineer in Ha Noi

Job Description and Requirements Alternate Job TitlesDesign Verification EngineerDigital Verification EngineerRTL Verification EngineerIP Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.What You'll Be DoingDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closureWrite test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverageDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and VerdiDrive coverage analysis and closure across code, functional, and assertion metricsParticipate in technical and peer reviews to ensure verification quality and process adherenceCollaborate with design, architecture, and silicon validation teams to identify and resolve issues earlyThe Impact You Will HaveEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applicationsReduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verificationContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliabilityEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IPStrengthen verification methodologies that scale across global engineering teamsMentor and elevate the skills of the Vietnam engineering team through knowledge sharingWhat You'll NeedBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field2+ years of hands-on design verification experience, ideally on digital or mixed-signal IPStrong proficiency with SystemVerilog, UVM, and industry-standard verification methodologiesExperience with VCS and Verdi for simulation and debugSolid understanding of verification planning, coverage-driven verification, and assertion-based verificationFamiliarity with formal verification tools like vc_formal is a plusScripting experience in Perl, TCL, or Python is a plusWho You AreYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptomYou can explain a complex verification failure to a design engineer in a way that gets them to the fix fasterYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestoneYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being askedYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test planThe Team You'll Be Part OfYou will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesDesign Verification EngineerDigital Verification EngineerRTL Verification EngineerIP Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.What You'll Be DoingDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closureWrite test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverageDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and VerdiDrive coverage analysis and closure across code, functional, and assertion metricsParticipate in technical and peer reviews to ensure verification quality and process adherenceCollaborate with design, architecture, and silicon validation teams to identify and resolve issues earlyThe Impact You Will HaveEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applicationsReduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verificationContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliabilityEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IPStrengthen verification methodologies that scale across global engineering teamsMentor and elevate the skills of the Vietnam engineering team through knowledge sharingWhat You'll NeedBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field2+ years of hands-on design verification experience, ideally on digital or mixed-signal IPStrong proficiency with SystemVerilog, UVM, and industry-standard verification methodologiesExperience with VCS and Verdi for simulation and debugSolid understanding of verification planning, coverage-driven verification, and assertion-based verificationFamiliarity with formal verification tools like vc_formal is a plusScripting experience in Perl, TCL, or Python is a plusWho You AreYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptomYou can explain a complex verification failure to a design engineer in a way that gets them to the fix fasterYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestoneYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being askedYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test planThe Team You'll Be Part OfYou will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements Alternate Job TitlesDesign Verification EngineerDigital Verification EngineerRTL Verification EngineerIP Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.What You'll Be DoingDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closureWrite test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverageDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and VerdiDrive coverage analysis and closure across code, functional, and assertion metricsParticipate in technical and peer reviews to ensure verification quality and process adherenceCollaborate with design, architecture, and silicon validation teams to identify and resolve issues earlyThe Impact You Will HaveEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applicationsReduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verificationContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliabilityEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IPStrengthen verification methodologies that scale across global engineering teamsMentor and elevate the skills of the Vietnam engineering team through knowledge sharingWhat You'll NeedBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field2+ years of hands-on design verification experience, ideally on digital or mixed-signal IPStrong proficiency with SystemVerilog, UVM, and industry-standard verification methodologiesExperience with VCS and Verdi for simulation and debugSolid understanding of verification planning, coverage-driven verification, and assertion-based verificationFamiliarity with formal verification tools like vc_formal is a plusScripting experience in Perl, TCL, or Python is a plusWho You AreYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptomYou can explain a complex verification failure to a design engineer in a way that gets them to the fix fasterYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestoneYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being askedYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test planThe Team You'll Be Part OfYou will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Job Description and RequirementsAlternate Job TitlesDesign Verification EngineerDigital Verification EngineerRTL Verification EngineerIP Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.What You'll Be DoingDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closureWrite test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverageDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and VerdiDrive coverage analysis and closure across code, functional, and assertion metricsParticipate in technical and peer reviews to ensure verification quality and process adherenceCollaborate with design, architecture, and silicon validation teams to identify and resolve issues earlyThe Impact You Will HaveEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applicationsReduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verificationContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliabilityEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IPStrengthen verification methodologies that scale across global engineering teamsMentor and elevate the skills of the Vietnam engineering team through knowledge sharingWhat You'll NeedBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field2+ years of hands-on design verification experience, ideally on digital or mixed-signal IPStrong proficiency with SystemVerilog, UVM, and industry-standard verification methodologiesExperience with VCS and Verdi for simulation and debugSolid understanding of verification planning, coverage-driven verification, and assertion-based verificationFamiliarity with formal verification tools like vc_formal is a plusScripting experience in Perl, TCL, or Python is a plusWho You AreYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptomYou can explain a complex verification failure to a design engineer in a way that gets them to the fix fasterYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestoneYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being askedYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test planThe Team You'll Be Part OfYou will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.Alternate Job TitlesDesign Verification EngineerDigital Verification EngineerRTL Verification EngineerIP Verification EngineerWe AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.What You'll Be DoingDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closureWrite test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverageDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and VerdiDrive coverage analysis and closure across code, functional, and assertion metricsParticipate in technical and peer reviews to ensure verification quality and process adherenceCollaborate with design, architecture, and silicon validation teams to identify and resolve issues earlyThe Impact You Will Have

Alternate Job Titles

Alternate Job TitlesAlternate Job Titles

• Design Verification Engineer

Design Verification EngineerDesign Verification Engineer

• Digital Verification Engineer

Digital Verification EngineerDigital Verification Engineer

• RTL Verification Engineer

RTL Verification EngineerRTL Verification Engineer

• IP Verification Engineer

IP Verification EngineerIP Verification Engineer

We Are

We AreWe Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You AreYou Are

You have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.

You have spent years proving that silicon actually works the way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn a tapeout into a respin, and building the infrastructure to catch those problems before they become expensive.You have spent years proving that siliconactually worksthe way the spec says it should, and you know the difference between a testbench that catches bugs and one that just makes coverage numbers look good. Verification is not a checkbox exercise for you. It is the discipline of thinking through every edge case, every protocol violation, every timing corner that could turn atapeoutinto arespin, and building the infrastructure to catch those problems before they become expensive.

You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.

You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers that actually fire when something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.You are comfortable reading a functional specification for a high-bandwidth interface IP and walking away with a mental model of where the risks live. From there, you build environments that stress those risks systematically, not randomly. You write checkers thatactually firewhen something breaks, and you know how to read a waveform in Verdi without spending three hours hunting for the root cause.

Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.

Mixed-signal verification does not scare you. Modeling real analog signals in SystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months of debug.Mixed-signal verification does not scare you. Modeling real analog signals inSystemVerilog, running co-simulations that blend RTL and real-world behavior, debugging across abstraction layers, this is the work you have done and the work you want to keep doing. You do not wait for someone to hand you a perfect test plan. You write one, you review it with the team, and you execute it with the kind of rigor that makes the difference between first-pass silicon success and months ofdebug.

At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.

At Synopsys, you will work on IP that powers the chips inside the devices changing how the world connects, computes, and moves.At Synopsys, you will work on IP that powers the chips inside thedeviceschanging how the world connects, computes, and moves.

What You'll Be Doing

What You'll Be DoingWhat You'll Be Doing

• Develop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure

Develop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closureDevelop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure

• Write test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverage

Write test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverageWrite test cases, assertions, and checkers inSystemVerilogto ensure comprehensive functional coverage

• Debug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi

Debug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and VerdiDebug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi

• Drive coverage analysis and closure across code, functional, and assertion metrics

Drive coverage analysis and closure across code, functional, and assertion metricsDrive coverage analysis and closure across code, functional, and assertion metrics

• Participate in technical and peer reviews to ensure verification quality and process adherence

Participate in technical and peer reviews to ensure verification quality and process adherenceParticipate in technical and peer reviews to ensure verification quality and process adherence

• Collaborate with design, architecture, and silicon validation teams to identify and resolve issues early

Collaborate with design, architecture, and silicon validation teams to identify and resolve issues earlyCollaborate with design, architecture, and silicon validation teams to identify and resolve issues early

The Impact You Will Have

The Impact You Will HaveThe Impact You Will HaveEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applicationsReduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verificationContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliabilityEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IPStrengthen verification methodologies that scale across global engineering teamsMentor and elevate the skills of the Vietnam engineering team through knowledge sharingWhat You'll NeedBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field2+ years of hands-on design verification experience, ideally on digital or mixed-signal IPStrong proficiency with SystemVerilog, UVM, and industry-standard verification methodologiesExperience with VCS and Verdi for simulation and debugSolid understanding of verification planning, coverage-driven verification, and assertion-based verificationFamiliarity with formal verification tools like vc_formal is a plusScripting experience in Perl, TCL, or Python is a plusWho You AreYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptomYou can explain a complex verification failure to a design engineer in a way that gets them to the fix fasterYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestoneYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being askedYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test plan

• Ensure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applications

Ensure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applicationsEnsure first-pass silicon success for high-bandwidth IP powering AI, 5G, cloud, and IoT applications

• Reduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verification

Reduce costly respins and post-silicon debug cycles by catching critical bugs early through rigorous verificationReduce costlyrespinsand post-silicon debug cycles by catching critical bugs early through rigorous verification

• Contribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliability

Contribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliabilityContribute to Synopsys maintaining its position as the world's leading IP provider through quality and reliability

• Enable faster time-to-market for customers building next-generation chips by delivering proven, validated IP

Enable faster time-to-market for customers building next-generation chips by delivering proven, validated IPEnable faster time-to-market for customers building next-generation chips by delivering proven, validated IP

• Strengthen verification methodologies that scale across global engineering teams

Strengthen verification methodologies that scale across global engineering teamsStrengthen verification methodologies that scale across global engineering teams

• Mentor and elevate the skills of the Vietnam engineering team through knowledge sharing

Mentor and elevate the skills of the Vietnam engineering team through knowledge sharingMentor and elevate the skills of the Vietnam engineering team through knowledge sharing

What You'll Need

What You'll NeedWhat You'll Need

• Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field

Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related fieldBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field

• 2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP

2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP

• Strong proficiency with SystemVerilog, UVM, and industry-standard verification methodologies

Strong proficiency with SystemVerilog, UVM, and industry-standard verification methodologiesStrong proficiency withSystemVerilog, UVM, and industry-standard verification methodologies

• Experience with VCS and Verdi for simulation and debug

Experience with VCS and Verdi for simulation and debugExperience with VCS and Verdi for simulation and debug

• Solid understanding of verification planning, coverage-driven verification, and assertion-based verification

Solid understanding of verification planning, coverage-driven verification, and assertion-based verificationSolid understanding of verification planning, coverage-driven verification, and assertion-based verification

• Familiarity with formal verification tools like vc_formal is a plus

Familiarity with formal verification tools like vc_formal is a plusFamiliarity with formal verification tools likevc_formalis a plus

• Scripting experience in Perl, TCL, or Python is a plus

Scripting experience in Perl, TCL, or Python is a plusScripting experience in Perl, TCL, or Python is a plus

Who You Are

Who You AreWho You Are

• You approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptom

You approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptomYou approach debugging like a detective, following the evidence in waveforms and logs until you find the root cause, not just the symptom

• You can explain a complex verification failure to a design engineer in a way that gets them to the fix faster

You can explain a complex verification failure to a design engineer in a way that gets them to the fix fasterYou can explain a complex verification failure to a design engineer in a way that gets them to the fix faster

• You are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestone

You are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestoneYou are accountable for your work and follow through on commitments, even when a coverage gap shows up two days before a milestone

• You thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being asked

You thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being askedYou thrive in collaborative environments and will help a teammate debug a tricky co-simulation issue without being asked

• You communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test plan

You communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test planYou communicate clearly in English, whether writing a bug report, presenting coverage results, or reviewing a test plan

The Team You'll Be Part Of

The Team You'll Be Part OfThe Team You'll Be Part Of

You will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.

You will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.You will join Synopsys Digital's R&D team in Hanoi, working on verification for high-bandwidth interface IP that ships to customers worldwide. The team is a mix of experienced engineers and growing talent, supported by global experts across the US, Europe, and Asia. You will have access to mentorship, technical training, and the opportunity to work on the complete design and verification flow from specification to silicon.

Rewards and Benefits

Rewards and BenefitsRewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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