ASIC Digital Design, Staff Engineer

ActiveVerified 2h ago

Job description

Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months. You are comfortable jumping between architecture discussions, Verilog coding sessions, and synthesis runs without losing sight of what you are building or why it matters. Believe that documentation is part of the design process, and you know how to write specs that both customers and your own team can actually use. You ask the right questions, clarify what is ambiguous, and move forward. At Synopsys, you will work on semiconductor IP that ships in products used across the industry, and the quality bar is high because it has to be. What You'll Be Doing * Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks* Participate in architecture exploration and contribute to design specifications that guide both implementation and verification* Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets* Support DFT and ATPG flows and coverage analysis* Generate high quality documents targeting different audiences: customer consumable and to support design implementation and verification teams.* Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps* Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality The Impact You Will Have * Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications* The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams* Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness* The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon* Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays* The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects* Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field* At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.* Solid understanding of DFT and ATPG methodologies* Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment* Fluency in English, both written and spoken, for documentation and cross-site collaboration* Experience with high-speed memory interfaces such as DDR/HBM is a strong plus Who You Are * You can take an architecture discussion and turn it into a design spec that both a customer and a verification engineer can work efficiently* When synthesis fails timing, you do not just push constraints around, you dig into the RTL, understand the critical path, and fix the root cause* You catch issues in code review that others miss because you are thinking about what happens downstream in gate-level simulation or in the lab* You are comfortable working across time zones with a global team, and you know how to communicate technical trade-offs clearly in writing and in meetings* You treat documentation as part of the deliverable, not an afterthought, and you take pride in specs that do not require constant clarification The Team You'll Be Part Of You will join the Synopsys FE Design team in Porto, part of a global organization responsible for designing and delivering semiconductor IP used across the industry. The team works on digital and mixed signal blocks that integrate into complex SoCs, and you will collaborate with engineers across design, verification, and product engineering sites worldwide. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months. You are comfortable jumping between architecture discussions, Verilog coding sessions, and synthesis runs without losing sight of what you are building or why it matters. Believe that documentation is part of the design process, and you know how to write specs that both customers and your own team can actually use. You ask the right questions, clarify what is ambiguous, and move forward. At Synopsys, you will work on semiconductor IP that ships in products used across the industry, and the quality bar is high because it has to be. What You'll Be Doing * Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks* Participate in architecture exploration and contribute to design specifications that guide both implementation and verification* Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets* Support DFT and ATPG flows and coverage analysis* Generate high quality documents targeting different audiences: customer consumable and to support design implementation and verification teams.* Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps* Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality The Impact You Will Have * Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications* The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams* Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness* The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon* Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays* The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects* Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field* At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.* Solid understanding of DFT and ATPG methodologies* Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment* Fluency in English, both written and spoken, for documentation and cross-site collaboration* Experience with high-speed memory interfaces such as DDR/HBM is a strong plus Who You Are * You can take an architecture discussion and turn it into a design spec that both a customer and a verification engineer can work efficiently* When synthesis fails timing, you do not just push constraints around, you dig into the RTL, understand the critical path, and fix the root cause* You catch issues in code review that others miss because you are thinking about what happens downstream in gate-level simulation or in the lab* You are comfortable working across time zones with a global team, and you know how to communicate technical trade-offs clearly in writing and in meetings* You treat documentation as part of the deliverable, not an afterthought, and you take pride in specs that do not require constant clarification The Team You'll Be Part Of You will join the Synopsys FE Design team in Porto, part of a global organization responsible for designing and delivering semiconductor IP used across the industry. The team works on digital and mixed signal blocks that integrate into complex SoCs, and you will collaborate with engineers across design, verification, and product engineering sites worldwide. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months. You are comfortable jumping between architecture discussions, Verilog coding sessions, and synthesis runs without losing sight of what you are building or why it matters. Believe that documentation is part of the design process, and you know how to write specs that both customers and your own team can actually use. You ask the right questions, clarify what is ambiguous, and move forward. At Synopsys, you will work on semiconductor IP that ships in products used across the industry, and the quality bar is high because it has to be. What You'll Be Doing * Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks* Participate in architecture exploration and contribute to design specifications that guide both implementation and verification* Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets* Support DFT and ATPG flows and coverage analysis* Generate high quality documents targeting different audiences: customer consumable and to support design implementation and verification teams.* Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps* Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality The Impact You Will Have * Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications* The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams* Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness* The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon* Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays* The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects* Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field* At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.* Solid understanding of DFT and ATPG methodologies* Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment* Fluency in English, both written and spoken, for documentation and cross-site collaboration* Experience with high-speed memory interfaces such as DDR/HBM is a strong plus Who You Are * You can take an architecture discussion and turn it into a design spec that both a customer and a verification engineer can work efficiently* When synthesis fails timing, you do not just push constraints around, you dig into the RTL, understand the critical path, and fix the root cause* You catch issues in code review that others miss because you are thinking about what happens downstream in gate-level simulation or in the lab* You are comfortable working across time zones with a global team, and you know how to communicate technical trade-offs clearly in writing and in meetings* You treat documentation as part of the deliverable, not an afterthought, and you take pride in specs that do not require constant clarification The Team You'll Be Part Of You will join the Synopsys FE Design team in Porto, part of a global organization responsible for designing and delivering semiconductor IP used across the industry. The team works on digital and mixed signal blocks that integrate into complex SoCs, and you will collaborate with engineers across design, verification, and product engineering sites worldwide. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.Job Description and RequirementsWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months. You are comfortable jumping between architecture discussions, Verilog coding sessions, and synthesis runs without losing sight of what you are building or why it matters. Believe that documentation is part of the design process, and you know how to write specs that both customers and your own team can actually use. You ask the right questions, clarify what is ambiguous, and move forward. At Synopsys, you will work on semiconductor IP that ships in products used across the industry, and the quality bar is high because it has to be. What You'll Be Doing * Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks* Participate in architecture exploration and contribute to design specifications that guide both implementation and verification* Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets* Support DFT and ATPG flows and coverage analysis* Generate high quality documents targeting different audiences: customer consumable and to support design implementation and verification teams.* Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps* Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality The Impact You Will Have * Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications* The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams* Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness* The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon* Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays* The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects* Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site What You'll Need * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field* At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.* Solid understanding of DFT and ATPG methodologies* Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment* Fluency in English, both written and spoken, for documentation and cross-site collaboration* Experience with high-speed memory interfaces such as DDR/HBM is a strong plus Who You Are * You can take an architecture discussion and turn it into a design spec that both a customer and a verification engineer can work efficiently* When synthesis fails timing, you do not just push constraints around, you dig into the RTL, understand the critical path, and fix the root cause* You catch issues in code review that others miss because you are thinking about what happens downstream in gate-level simulation or in the lab* You are comfortable working across time zones with a global team, and you know how to communicate technical trade-offs clearly in writing and in meetings* You treat documentation as part of the deliverable, not an afterthought, and you take pride in specs that do not require constant clarification The Team You'll Be Part Of You will join the Synopsys FE Design team in Porto, part of a global organization responsible for designing and delivering semiconductor IP used across the industry. The team works on digital and mixed signal blocks that integrate into complex SoCs, and you will collaborate with engineers across design, verification, and product engineering sites worldwide. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

We Are

We AreWe Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You AreYou Are

You have at least 3 years of hands-on experience in digital design, writing RTL that has to synthesize cleanly, meet timing, and actually work in silicon. You know the difference between code that passes lint and code that makes the verification activities easier in the next months.

You are comfortable jumping between architecture discussions, Verilog coding sessions, and synthesis runs without losing sight of what you are building or why it matters. Believe that documentation is part of the design process, and you know how to write specs that both customers and your own team can actually use. You ask the right questions, clarify what is ambiguous, and move forward.

At Synopsys, you will work on semiconductor IP that ships in products used across the industry, and the quality bar is high because it has to be.

What You'll Be Doing

What You'll Be DoingWhat You'll Be Doing

* Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks

* Participate in architecture exploration and contribute to design specifications that guide both implementation and verification

* Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets

* Support DFT and ATPG flows and coverage analysis

* Generate high quality documents targeting different audiences: customer consumable and to support design implementation and verification teams.

* Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps

* Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality

The Impact You Will Have

The Impact You Will HaveThe Impact You Will Have

* Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications

* The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams

* Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness

* The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon

* Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays

* The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects

* Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site

What You'll Need

What You'll NeedWhat You'll Need

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field

* At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows

* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.

* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.

* Solid understanding of DFT and ATPG methodologies

* Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment

* Fluency in English, both written and spoken, for documentation and cross-site collaboration

* Experience with high-speed memory interfaces such as DDR/HBM is a strong plus

Who You Are

Who You AreWho You Are

* You can take an architecture discussion and turn it into a design spec that both a customer and a verification engineer can work efficiently

* When synthesis fails timing, you do not just push constraints around, you dig into the RTL, understand the critical path, and fix the root cause

* You catch issues in code review that others miss because you are thinking about what happens downstream in gate-level simulation or in the lab

* You are comfortable working across time zones with a global team, and you know how to communicate technical trade-offs clearly in writing and in meetings

* You treat documentation as part of the deliverable, not an afterthought, and you take pride in specs that do not require constant clarification

The Team You'll Be Part Of

The Team You'll Be Part OfThe Team You'll Be Part Of

You will join the Synopsys FE Design team in Porto, part of a global organization responsible for designing and delivering semiconductor IP used across the industry. The team works on digital and mixed signal blocks that integrate into complex SoCs, and you will collaborate with engineers across design, verification, and product engineering sites worldwide.

Rewards and Benefits

Rewards and BenefitsRewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Verified 4d agoPosted last month