Advanced Packaging Technology and Service Engineer (APTS)-身心障礙人才招募

TSMCLocation Taiwan

ActiveVerified 6h ago

Job description

Company Taiwan Semiconductor Manufacturing Company Limited Location Taiwan Career Area Accessibility Inclusion Job Type Engineer / Admin Employment Type Regular Posted Mar 17, 2026 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of over 17 million 12-inch equivalent wafers in 2025. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Taiwan Semiconductor Manufacturing Company (TSMC) is dedicated to fostering a friendly and inclusive work environment while actively safeguarding the employment rights of individuals with accessabilities. In compliance with the "People with Disabilities Rights Protection Act," we have specially designed a dedicated talent portal for individuals with accessabilities. We sincerely welcome candidates holding valid disability identification to join TSMC and work with us to shape the future of technology! Job Responsibilities TSMC's advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc.This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration.TSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution.TSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields.TSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production. Job Qualifications 1. Bachelor's degree or above in Electrical/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields.2. Solid technical understanding of semiconductor testing concept.3. Familiar with programming language.4. Hands-on participation and a strong sense of ownership.5. Fluent in English and exhibit good communication skills to work within cross-functional teams.6. A valid disability identification issued in Taiwan is required.#LI-DNI TSMC Core Values At TSMC, we invite talented individuals who share our vision and values to contribute to our continued success. Our core values are the foundation of our culture, guiding every decision and action. We seek applicants who deeply resonate with these principles and embody them in their work: Integrity: Tell the truth. We do not brag. We do not make commitments lightly. Once we make a commitment, we devote ourselves completely to meeting that commitment.Commitment: Employees are dedicated to the company, view the company’s success as their own and work diligently to make their best contributions. As commitment is mutual, the Company strives to serve the best interests of its employees. Innovation: Innovation is the wellspring of the Company's growth. It means more than new ideas; it means putting ideas into practice. Customer Trust: We strive to build deep and enduring relationships with our customers, who trust and rely on us to be part of their success over the long term. (For more details on TSMC’s Core Values, please visit：https://www.tsmc.com/english/aboutTSMC/values) Fostering a global inclusive workplace reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to global inclusive workplace allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. We strive to create a workplace that is equitable and accessible to all employees. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers. Back to job list Apply Share Email Facebook LinkedIn X // Select all anchor elements that have a jobId in their href const anchors = document.querySelectorAll('.custom-links a[href*="jobId="]'); const URLSource = window.location.href.match(/source=([^&]+)/)[1]; const URLTags = window.location.href.match(/tags=([^&]+)/)[1]; // Loop through each matching anchor element anchors.forEach(anchor => { // Get the current href of the anchor const href = anchor.getAttribute('href'); // Extract the jobId using a regular expression const jobIdMatch = href.match(/jobId=(\d+)/); const hasCareersPath = href.match(/\/careers\//); if (jobIdMatch) { const jobId = jobIdMatch[1]; // Capture the jobId value // Construct the new href with the extracted jobId const newHrefStart = anchor.getAttribute("href").split("?")[0], newHref = newHrefStart + `?jobId=${jobId}&source=${URLSource}&tags=${URLTags}`; // Set the new href attribute anchor.setAttribute('href', newHref); } }); { "@context": "http://schema.org", "@type": "JobPosting", "datePosted": null, "description": "\u003Cdiv\u003ETaiwan Semiconductor Manufacturing Company (TSMC) is dedicated to fostering a friendly and inclusive work environment while actively safeguarding the employment rights of individuals with accessabilities. In compliance with the \"People with Disabilities Rights Protection Act,\" we have specially designed a dedicated talent portal for individuals with accessabilities. We sincerely welcome candidates holding valid disability identification to join TSMC and work with us to shape the future of technology!\u003C\/div\u003E", "employmentType": ["Regular"], "hiringOrganization" : { "@type": "Organization", "name": "TSMC - Taiwan Semiconductor Manufacturing Company Limited", "url": "https://careers.tsmc.com/en_US/careers", "logo": "https://careers.tsmc.com/_cms/6/image/logoHiringOrganization/1?version=269513", "sameAs": "https:\/\/www.tsmc.com\/english" }, "identifier": { "value": 19399, "@type": "PropertyValue" }, "jobLocation" : { "@type": "Place", "address": { "streetAddress": "Taiwan", "@type": "PostalAddress" } }, "educationRequirements": "\u003Cdiv\u003E1. Bachelor's degree or above in Electrical\/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields.\u003C\/div\u003E\u003Cdiv\u003E2. Solid technical understanding of semiconductor testing concept.\u003C\/div\u003E\u003Cdiv\u003E3. Familiar with programming language.\u003C\/div\u003E\u003Cdiv\u003E4. Hands-on participation and a strong sense of ownership.\u003C\/div\u003E\u003Cdiv\u003E5. Fluent in English and exhibit good communication skills to work within cross-functional teams.\u003C\/div\u003E\u003Cdiv\u003E6. A valid disability identification issued in Taiwan is required.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cfont color=\"#ffffff\"\u003E#LI-DNI\u003C\/font\u003E\u003C\/div\u003E", "experienceRequirements": "\u003Cdiv\u003E1. Bachelor's degree or above in Electrical\/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields.\u003C\/div\u003E\u003Cdiv\u003E2. Solid technical understanding of semiconductor testing concept.\u003C\/div\u003E\u003Cdiv\u003E3. Familiar with programming language.\u003C\/div\u003E\u003Cdiv\u003E4. Hands-on participation and a strong sense of ownership.\u003C\/div\u003E\u003Cdiv\u003E5. Fluent in English and exhibit good communication skills to work within cross-functional teams.\u003C\/div\u003E\u003Cdiv\u003E6. A valid disability identification issued in Taiwan is required.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cfont color=\"#ffffff\"\u003E#LI-DNI\u003C\/font\u003E\u003C\/div\u003E", "workHours": "\u003Cdiv\u003ETSMC's advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003EThis technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003ETSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003ETSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003ETSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.\u003C\/div\u003E", "qualifications": "\u003Cdiv\u003E1. Bachelor's degree or above in Electrical\/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields.\u003C\/div\u003E\u003Cdiv\u003E2. Solid technical understanding of semiconductor testing concept.\u003C\/div\u003E\u003Cdiv\u003E3. Familiar with programming language.\u003C\/div\u003E\u003Cdiv\u003E4. Hands-on participation and a strong sense of ownership.\u003C\/div\u003E\u003Cdiv\u003E5. Fluent in English and exhibit good communication skills to work within cross-functional teams.\u003C\/div\u003E\u003Cdiv\u003E6. A valid disability identification issued in Taiwan is required.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cfont color=\"#ffffff\"\u003E#LI-DNI\u003C\/font\u003E\u003C\/div\u003E", "responsibilities": "\u003Cdiv\u003ETSMC's advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003EThis technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003ETSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003ETSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003ETSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.\u003C\/div\u003E", "skills": "\u003Cdiv\u003E1. Bachelor's degree or above in Electrical\/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields.\u003C\/div\u003E\u003Cdiv\u003E2. Solid technical understanding of semiconductor testing concept.\u003C\/div\u003E\u003Cdiv\u003E3. Familiar with programming language.\u003C\/div\u003E\u003Cdiv\u003E4. Hands-on participation and a strong sense of ownership.\u003C\/div\u003E\u003Cdiv\u003E5. Fluent in English and exhibit good communication skills to work within cross-functional teams.\u003C\/div\u003E\u003Cdiv\u003E6. A valid disability identification issued in Taiwan is required.\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cbr\u003E\u003C\/div\u003E\u003Cdiv\u003E\u003Cfont color=\"#ffffff\"\u003E#LI-DNI\u003C\/font\u003E\u003C\/div\u003E", "title" : "Advanced Packaging Technology and Service Engineer (APTS)-\u8eab\u5fc3\u969c\u7919\u4eba\u624d\u62db\u52df" }

Company Taiwan Semiconductor Manufacturing Company Limited Location Taiwan Career Area Accessibility Inclusion Job Type Engineer / Admin Employment Type Regular Posted Mar 17, 2026

Company Taiwan Semiconductor Manufacturing Company Limited

Company

Taiwan Semiconductor Manufacturing Company Limited

Location Taiwan

Location

Taiwan

Career Area Accessibility Inclusion

Career Area

Accessibility Inclusion

Job Type Engineer / Admin

Job Type

Engineer / Admin

Employment Type Regular

Employment Type

Regular

Posted Mar 17, 2026

Posted

Mar 17, 2026

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. As of 2024, TSMC serves more than 500 customers and manufactures over 11,000 products for high-performance computing, smartphones, the Internet of Things (IoT), automotive, and digital consumer electronics. It is the world’s largest provider of logic ICs, with an annual capacity of over 17 million 12-inch equivalent wafers in 2025. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and the Company began construction on a specialty technology fab in Dresden, Germany, in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade.

Taiwan Semiconductor Manufacturing Company (TSMC) is dedicated to fostering a friendly and inclusive work environment while actively safeguarding the employment rights of individuals with accessabilities. In compliance with the "People with Disabilities Rights Protection Act," we have specially designed a dedicated talent portal for individuals with accessabilities. We sincerely welcome candidates holding valid disability identification to join TSMC and work with us to shape the future of technology!

Job Responsibilities TSMC's advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc.This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration.TSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution.TSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields.TSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.

Job Responsibilities

TSMC's advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc.This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration.TSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution.TSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields.TSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.

This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration.

TSMC's packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution.

TSMC's advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields.

TSMC's advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production.

Job Qualifications 1. Bachelor's degree or above in Electrical/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields.2. Solid technical understanding of semiconductor testing concept.3. Familiar with programming language.4. Hands-on participation and a strong sense of ownership.5. Fluent in English and exhibit good communication skills to work within cross-functional teams.6. A valid disability identification issued in Taiwan is required.#LI-DNI